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An Automatic Node Removal Method for Approximate Computation of Circuits

A technology of approximate calculation and node deletion, applied in calculation, computer-aided design, electrical digital data processing, etc., can solve the problems of no node deletion process, failure to take into account errors, circuit delays, power consumption, etc., to improve design efficiency, The effect of expanding the scope of application

Inactive Publication Date: 2020-11-27
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] What the present invention aims to solve is to provide a method that can achieve high precision and low error for the above-mentioned traditional approximate calculation method that requires manual unit design, cannot take into account errors, circuit delays, and power consumption at the same time, and has no indicators to guide the node deletion process. The automatic node deletion method adopts the automatic loop iteration method to self-assess the priority of deleting each node in the circuit, which reduces the manual design time and improves the effect of node deletion on circuit performance

Method used

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  • An Automatic Node Removal Method for Approximate Computation of Circuits
  • An Automatic Node Removal Method for Approximate Computation of Circuits
  • An Automatic Node Removal Method for Approximate Computation of Circuits

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Embodiment Construction

[0029] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0030] The present invention provides an automatic node deletion method for circuit approximation calculation, after a short period of iteration and simulation, the optimal approximation calculation is achieved by adopting a cell sorting method with an optimal energy-delay product and error ratio .

[0031] Such as figure 2 Shown is the structural diagram of applying the automatic node deletion method provided by the present invention to realize approximate calculation in the embodiment, including an information collection module, a data analysis module, a node deletion module and a synthesis and simulation module, and the information collection module is used to collect the synthesis and simulation module The circuit data information generated in and passed to the data analysis module; the data analysis module is used to analyze, process a...

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Abstract

The invention relates to an automatic node deletion method for circuit approximate calculation, which belongs to the technical field of integrated circuits. Synthesize the circuit that needs approximate calculation to obtain the circuit netlist and obtain the power consumption and delay information in the circuit netlist, and obtain the circuit output error through simulation; if the error reaches the threshold, the circuit netlist is output, if not, the circuit netlist is separately Each node in the table is deleted one by one to obtain the power consumption change value, delay change value and output error change value of the circuit when each node is deleted; calculate the power consumption change value and delay change value of each node when the node is deleted The ratio to the output error change value is marked on each node, and the nodes in the circuit netlist are sorted in the order of the ratio from high to low; delete the node with the highest ratio and the affiliated node that is only used to generate the node, and the node will be deleted Synthesize the final circuit netlist to generate a new circuit netlist and return to the first step. The invention has the characteristics of high efficiency, high precision and low error.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an automatic node deletion method for circuit approximate calculation. Background technique [0002] Over the past few decades, process linewidth has been a key technology in the development of integrated circuits. However, as the shrinking of line width is difficult to continue, Moore's Law gradually begins to fail, coupled with changes in process, voltage, temperature (PVT) and shrinking of threshold, the further improvement of circuit performance and power consumption is greatly limited. At the same time, the reduction of the line width increases the power density, and the heat dissipation of the integrated circuit becomes difficult. In order to solve this problem, approximate computing technology is widely used in various integrated circuit designs, from hardware design to algorithms and different abstraction layers at the software level, and has beco...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/392
CPCG06F30/392
Inventor 贺雅娟张子骥何进衣溪林史兴荣张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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