Dual-node-upset-resistant D latch applied to high-frequency circuit

Abstract

The invention discloses a dual-node-upset-resistant D latch applied to a high-frequency circuit, which belongs to the field of anti-core reinforcement in reliability of integrated circuits. The problems that a traditional D latch resistant to charge sharing needs to consume more hardware and is large in power consumption and area, and the reinforcement performance is seriously affected due to moresensitive nodes are solved. The D latch comprises 20 NMOS transistors N1 to N20 and 12 PMOS transistors P1 to P12, and only 32 transistors are needed to construct the D latch, so that the area andthe power consumption overhead of the D latch are reduced. An input signal D can be directly transmitted to the output end of an output signal D through the transmission gates constructed by the transistors N20 and P12, so that the transmission delay is reduced. The D latch provided by the invention is suitable for being applied to high-frequency circuits, and is particularly suitable for aerospace, aerospace flight, nuclear power stations and the like with nuclear radiation effects.

Description

technical field [0001] The invention belongs to the field of anti-nuclear hardening in integrated circuit reliability. Background technique [0002] D latches are widely used in various digital integrated circuits, such as decoders and timing control circuits. However, since the latch has the function of storing information, radiation particles will change the information it holds, thus causing errors in the electronic system. With the advancement of integrated circuit technology, due to the influence of charge sharing, the flipping phenomenon has changed from the previous flipping of one node to the flipping of two nodes. However, the existing anti-charge sharing D latch requires more than 70 transistors, which requires more hardware, has a larger area and power consumption, and has more than 10 sensitive nodes. The more sensitive nodes, the more nodes are blocked. The higher the attack probability, the worse the reliability of the system, which seriously affects the hard...

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to solve the problem that the traditional anti-charge sharing D-latch consumes more hardware, consumes more power consumption and area, and seriously affects the reinforcement performance due to more sensitive nodes. The present invention provides a A D-Latch Anti-Double-Node Flip for High-Frequency Circuit Applications

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