D latch with layout symmetry and resistance to three-node upset

A technology of latches and symmetry, applied in the direction of reliability improvement modification, logic circuit coupling/interface using field effect transistors, logic circuit connection/interface layout, etc., can solve multi-hardware, high power consumption, large area, etc. question

Pending Publication Date: 2020-06-05
ZHONGBEI UNIV
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Problems solved by technology

[0005] The present invention is to solve the problems that the existing anti-three-node flipping D latch requires more hardware, h

Method used

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  • D latch with layout symmetry and resistance to three-node upset
  • D latch with layout symmetry and resistance to three-node upset

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Embodiment Construction

[0069] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0070] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0071] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0072] see figure 1 Describe this embodiment mode. The three-node flip-resistant D-latch with layout symme...

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Abstract

The invention discloses a D latch with layout symmetry and resistance to three-node upset, and belongs to the field of anti-core reinforcement in reliability of integrated circuits. The problems thatan existing anti-three-node-overturn D latch needs to consume more hardware, and is high in power consumption and large in area are solved. The D latch comprises 44 NMOS transistors N1 to N44 and 20 PMOS transistors P1 to P20; and the transistors N1 to N16 and the transistors P1 to P8 form a unit 1, the transistors N17 to N32 and the PMOS transistors P9 to P16 form a unit 2, and the unit 1 and theunit 2 are mirror images of each other in circuit structure. Two units which are connected in a crossed mode are used for achieving recovery of overturning of all the three nodes. The D latch is mainly suitable for medium-low frequency circuits with low power consumption.

Description

technical field [0001] The invention belongs to the field of anti-nuclear hardening in integrated circuit reliability. Background technique [0002] In recent years, my country's aerospace industry is developing rapidly. From the Shenzhou series of spacecraft to the Beidou satellite navigation system, to the Tiangong series of space laboratories, to the Chang'e series of probes and the Yutu series of lunar rovers, this means that my country's exploration of space is getting wider and wider. Manned spaceflight, satellite remote sensing communication and positioning, space docking and lunar exploration, my country's application and demand for aerospace technology is also increasing. For an integrated circuit working in a space environment, it is not only required to have the normal working performance of the integrated circuit, but also to be able to adapt to various radiation environments in space. Therefore, the design of latches with high performance and stable radiation ...

Claims

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Application Information

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IPC IPC(8): H03K19/003H03K19/0185
CPCH03K19/003H03K19/0185
Inventor 杜芳芳郭靖
Owner ZHONGBEI UNIV
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