87 results about "Neural processing" patented technology

Disclosed is a digital neural processor comprising at least one neural processing element. The neural processing elements including at least one simulated dendrite and a simulated axon. Each of the simulated dendrites may include: a dendrite input capable of receiving at least one dendrite input signal and a dendrite signal propagation function capable of calculating a dendrite output signal in discrete time steps from each dendrite input signal. The signal propagation function may further include a delay parameter; a duration parameter; and an amplitude parameter. The simulated axon includes an axon input capable of receiving dendrite output signals, an axon function, capable of calculating an axon output signal from dendrite output signal(s) and an axon output capable of outputting the axon output signal.

Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

A system for intelligent goal-directed search in large volume visual imagery using a cognitive-neural subsystem is disclosed. The system comprises an imager, a display, a display processor, a cognitive-neural subsystem, a system controller, and operator controls. The cognitive-neural subsystem comprises a cognitive module, a neural module, and an adaptation module. The cognitive module is configured to extract a set of regions of interest from the image using a cognitive algorithm. The neural module is configured to refine the set of regions of interest using a neural processing algorithm. The adaptation module is configured to bias the cognitive algorithm with information gained from the neural module to improve future searches. The system functions in a plurality of operating modes, including: batch mode, semi-interactive mode, real-time mode, and roaming mode.

Embodiments relate to a neural processor circuit that includes a kernel access circuit and multiple neural engine circuits. The kernel access circuit reads compressed kernel data from memory external to the neural processor circuit. Each neural engine circuit receives compressed kernel data from the kernel access circuit. Each neural engine circuit includes a kernel extract circuit and a kernel multiply-add (MAD) circuit. The kernel extract circuit extracts uncompressed kernel data from the compressed kernel data. The kernel MAD circuit receives the uncompressed kernel data from the kernel extract circuit and performs neural network operations on a portion of input data using the uncompressed kernel data.

The present invention discloses an integrated neuro-processor comprising at least a three-dimensional memory (3D-M) array. The 3D-M array stores the synaptic weights, while the neuro-processing circuit performs neural processing. The 3-D integration between the 3D-M array and the neuro-processing circuit not only improves the computational power per die area, but also greatly increases the storage capacity per die area.

Systems and methods to process packets of information use an on-chip information processing system configured to receive, resolve, convert, and/or transmit packets of different packet-types in accordance with different protocols. A first packet-type may use a protocol for wired local-area-networking (LAN) technologies, such as Ethernet. A second packet-type may use a proprietary protocol. The proprietary protocol may be used to exchange information with one or more packet processing engines, such as neural processing engines.

A vertically integrated neuro-processor comprises a plurality of neural storage-processing units (NSPU's). Each NSPU comprises at least a neuro-storage circuit and a neuro-processing circuit. The neuro-storage circuit comprises a memory array for storing at least a synaptic weight, while the neuro-processing circuit performs neural processing with the synaptic weight. The memory array and the neuro-processing circuit are vertically stacked and communicatively coupled by a plurality of inter-level connections.

The invention relates to a multi-charge coupled device group self-adaptive imaging instrument of a cambered optical structure and a method thereof, belonging to a field of the image information acquisition and processing. By imitating an ommateum to adjust the nerve conduction mode with the change of the illumination under the condition of day alternates with night to obtain a self-adaptive imaging effect principle, the instrument uses a plurality of common charge coupled devices (CCD), corresponding auxiliary circuits and a neural processing algorithm to construct a biomimic self-adaptive adjustment imaging instrument. The imaging instrument has an imaging function of self adjusting fusion modes with the change of illumination conditions, can acquire a high-contrast image under a normal illumination condition, and also can acquire a high-brightness sensitive image under a weak illumination condition. The invention realizes high-definition surveillance and monitoring under the condition of day alternates with night, belonging to the image information acquisition and processing field.

A neural processor includes one or more neural engine circuits and a planar engine circuit. The neural engine circuits can perform convolution operations of first input data with one or more kernels to generate a first output. The planar engine circuit receives second input data that corresponds to a version of the first input data. The planar engine circuit also receives third input data that includes fourth input data and fifth input data stored together in a dimension of third input data. The planar engine circuit performs a first elementwise operation between a version of the second input data and a version of the fourth input data to generate intermediate data. The planar engine circuit performs a second elementwise operation between the intermediate data and a version of the fifth input data to generate a second output.

A packet-network analyzer system for characterizing network conditions of a packet-network-under-test is provided. In this regard, one such system can be broadly summarized by a representative analyzer system that incorporates a data collection element to receive the raw digital data from a host analyzer, a data selection element to generate a selected data set from the raw digital data, a data processing element to process the selected data set to generate a normalized data set, a neural processing module to process the normalized data set to generate a set of rules and relationships, and a data mining module that uses the rules and relationships to generate a mined data set from the selected data set, the mined data set being used to characterize a packet-network-under-test. Another embodiment can be described as a method for analyzing a packet-network-under-test, comprising the steps of receiving raw digital data that is derived from a packet-network-under-test; generating a selected data set from the received raw digital data; generating a normalized data set from the selected data set; processing the normalized data set in a neural network to generate a set of rules and relationships; using the set of rules and relationships for mining the selected data set to generate a mined data set; and using the mined data set to characterize the packet-network-under-test.

Embodiments of the present disclosure relate to splitting input data into smaller units for loading into a data buffer and neural engines in a neural processor circuit for performing neural network operations. The input data of a large size is split into slices and each slice is again split into tiles. The tile is uploaded from an external source to a data buffer inside the neural processor circuit but outside the neural engines. Each tile is again split into work units sized for storing in an input buffer circuit inside each neural engine. The input data stored in the data buffer and the input buffer circuit is reused by the neural engines to reduce re-fetching of input data. Operations of splitting the input data are performed at various components of the neural processor circuit under the management of rasterizers provided in these components.

Methods and apparatus for piecewise linear neuron modeling and implementing one or more artificial neurons in an artificial nervous system based on one or more linearized neuron models. One example method (for implementing a combination of a plurality of neuron models in a system of neural processing units) generally includes loading parameters for a first neuron model selected from the plurality of neuron models into a first neural processing unit, determining a first state of the first neural processing unit based at least in part on the parameters for the first neuron model, and determining a second state of the first neural processing unit based at least in part on the parameters for the first neuron model and on the first state. This method may also include updating the plurality of neuron models (e.g., by adding, deleting, or adjusting parameters for the first neuron model or another neuron model).

Embodiments relate to a neural processor circuit that includes a first number of neural engine circuits, a second number of channels and a data processor circuit. The first number of neural engine circuits are pipelined into the second number of chains smaller than the first number. Each of the chains is configured to generate output data of a first size. Each of the channels is coupled to each of the chains and configured to transmit the output data from each of the neural engine circuits in the chains sequentially. The data processor circuit is coupled to the channels to receive the output data. The data processor circuit aggregates the output data of each of the chains into aggregated data of a second size larger than the first size and writes the aggregated data of the second size into a buffer memory of the data processor circuit.

The invention relates to a product image recognition method based on EEG signal and fuzzy inference. The method comprises the following steps: 1) image evaluation is carried out on the product image which needs to be recognized by using EEG signal acquisition device; 2) the classification number of perceptual image vocabulary pair is set, and the image words of the pictures are judged; 3) according to the image reasoning model, the required behavior and EEG data are statistically analyzed; 4) that fuzzy matrix is substituted into the calculation to carry on the comprehensive evaluation. The invention has the beneficial effects that: the invention starts from the neural processing mechanism, searches for the mapping relationship between the image and the EEG, reasoning the product image byusing the EEG experiment combined with fuzzy evaluation, and constructs a new product image quantitative reasoning method; The product image reasoning model based on EEG can directly calculate the semantic value of the subjective image of the product samples through the objective data (the selection rate of the subjects, reaction time and N400 amplitude) rather than subjective evaluation, which can provide methodological support for the future systematic image acquisition.

Embodiments relate to a denominator circuit that determines the number of valid elements of a data surface covered by a kernel depending on various locations of the kernel relative to the data surface. The denominator circuit includes a first circuit and a second circuit that have the same structure. The first circuit receives numbers representing different horizontal locations of a reference point in the kernel and generates a first matrix with first output elements corresponding to the different horizontal locations. The second circuit receives numbers representing different vertical locations of a reference point in the kernel and generates a second matrix with second output elements corresponding to the different vertical locations. A matrix multiplication of the first matrix and the second matrix is performed to obtain an array of valid elements covered by the kernel.

A neural processing unit (NPU), a method for driving an artificial neural network (ANN) model, and an ANN driving apparatus are provided. The NPU includes a semiconductor circuit that includes at least one processing element (PE) configured to process an operation of an artificial neural network (ANN) model; and at least one memory configurable to store a first kernel and a first kernel filter. The NPU is configured to generate a first modulation kernel based on the first kernel and the first kernel filter and to generate second modulation kernel based on the first kernel and a second kernel filter generated by applying a mathematical function to the first kernel filter. Power consumption and memory read time are both reduced by decreasing the data size of a kernel read from a separate memory to an artificial neural network processor and/or by decreasing the number of memory read requests.