244 results about "Neural processing" patented technology

A system for real-time detection and mitigation of morphing malware in high-density edge networks, consisting of: a data acquisition unit configured to receive, normalize, and encode multimodal telemetry data streams originating from at least one of the following domains: network traffic, process behavior, system call sequences, binary instruction traces, and control flow graphs; the data acquisition unit is further configured to compute feature embeddings over sliding time windows and apply privacy-preserving redactions prior to storage; a generative neural processor that is operationally coupled to the data acquisition unit and configured to generate synthetic morphing malware variants by learning probabilistic transformations of previously observed malicious data representations, maintaining semantic functionality while varying structural and behavioral features; a discriminative neural processor trained adversarially with the generative neural processor, wherein the discriminative neural processor is configured to detect morphing malware by evaluating a probability distribution over multimodal telemetry embeddings and classifying anomalous process and flow behaviors in real time; a coordination processor that is communicatively connected to both the generative neural processor and the discriminative neural processor and is configured to orchestrate adversarial co-training, regulate detection thresholds, calculate reinforcement-based penalties for false negative results, and trigger countermeasures as soon as a detection confidence level exceeds a predefined adaptive threshold; a secure, system-integrated inference and enforcement unit configured to perform low-latency countermeasures at the network edge, including selective packet filtering, flow isolation, process interruption, or system microsegmentation, based on instructions from the coordinating processor; and a hardware-embedded security enclave that is embedded in the system and configured to store cryptographic keys, neural model parameters, and integrity affirmation data to ensure the confidentiality, authenticity, and immutability of model artifacts and policy configurations.

According to one example of the present disclosure, the neural processing unit may comprise a processing element array configured to perform operations of a neural network model and a post-processing unit configured to process data output from the processing element array. The post-processing unit includes a first computation circuit that extracts a subset of classes for each bounding box by comparing class scores of classes and a second computation circuit configured to extract one or more bounding boxes by comparing a class confidence score of each bounding box with a threshold confidence score.

The invention discloses an awareness perception quantum gravitational nerve acceleration unified computing platform and method based on formalized verification, and belongs to the field of high-performance computing, medical AI and quantum information processing. A quantum gravitational coupling neural processing unit (QGCNPU); a consciousness information integral calculation core (phi ICC); formalizing a receipt chain verifier (FRCV); and the mirror reflection symmetry correction module (MRSCM) is used for eliminating the continuous projection mistake and the discrete Boolean mistake through topological equivalence verification of a local observer and a global GodCam visual angle. The system adopts an FPGA + ASIC + quantum processor three-layer heterogeneous architecture, and supports real-time pathological modeling (precision gt; gt) of neurodegenerative diseases such as Alzheimer's disease, Parkinson's disease and ALS; 99.7%), drug target discovery (acceleration by 50 times) and consciousness state monitoring (time resolution lt; and meanwhile, the mathematical proving performance and the clinical auditing performance of the calculation process are ensured, and the requirements of the global 152 billion dollar neural science and technology market and the 89 billion dollar quantum calculation industry are met.

Devices and techniques are generally described for nonlinear tensor compression for neural networks. In various examples, a first tensor associated with a first layer of a neural network may be determined. One or more neural processing units of accelerator hardware may generate a first compressed tensor by applying a nonlinear compression function to the first tensor. The first compressed tensor may be stored in a first memory of the one or more computer-readable media. A first operation associated with a second layer of the neural network may be determined, where the first operation uses output of the first layer. The first operation may be performed based on the first compressed tensor.

A docking station includes a processor and a memory coupled to the processor. The docking station may be configured to establish a sideband connection between an information handling system and the docking station subsequent to detecting the information handling system docking at the docking station. The docking station may also execute a workload of the information handling system, subsequent to the establishment of the sideband connection. In addition, the docking station may transmit a notification to resume the workload via the sideband connection subsequent to detecting that the information handling system is undocked from the docking station while performing the executing of the workload.

A method may comprise receiving a first neural network (NN) model including one or more functions; generating a second NN model in a form of directed acyclic graph (DAG) including one or more graph modules by converting the one or more functions; calculating one or more scale values by obtaining maximum and minimum values of parameters input to the one or more graph modules; updating the parameters based on the one or more scale values; and generating a third NN model, in a form of machine code executable on a particular neural processing unit, including the updated parameters.

Example storage systems, storage devices, and methods provide peer configuration of hardware compute resources among peer storage devices. Data storage devices may include hardware circuits, such as graphics processor units, media processor circuits, compute accelerator circuits, and neural processing units, configured for compute operations targeting host data associated with that storage device. One of the storage devices is configured to act as a master storage device for determining firmware configurations for the other storage devices and sending an indication of the firmware image to be used for some operating period. The storage device receiving the firmware image loads the firmware image for the hardware circuit and reboots the hardware circuit to configure it with the firmware image.

A heterogeneous neural processing system includes a first processor configured to perform encoding and decoding operations of an autoencoder, and a second processor configured to perform neural network operations of a particular task, the operations having iterative processing. The processors perform compute tasks through synchronous data exchange to implement a generative AI model. The first processor processes a feature map divided into data rows, caches the data into active memory using row-based depth-first scheduling, and selects deeper operations in the network hierarchy when processing branch inputs, outputs, and residual connections. And H reuses boundary pixels between the cache storage space segments, so that convolution and element-level operation can be executed simultaneously. A neural network adjusts the device analysis model to identify layer dependencies, applies search space constraints, performs an iterative search to generate a fusion plan, and selects an optimal plan based on external memory access and execution delays.

Disclosed in the embodiments of the present application are a processor, a computing node, and a computing cluster, which are used for simplifying the network architecture of the computing cluster. The processor comprises: a general-purpose protocol port, which is used for supporting a first communication protocol and a second communication protocol, wherein the second communication protocol is different from the first communication protocol; the first communication protocol is a communication protocol of a first network, the second communication protocol is a communication protocol of a second network, the first network is used for supporting communication between a plurality of processors in one computing node including the processor, the second network is used for supporting communication between the processor and other processors comprised in other computing nodes, and the processor is any one of a graphics processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPU) and a general-purpose graphics processing unit (GPGPU).

A computing device includes at least one processor, one or more non-transitory computer-readable storage media, a system for fine-tuning a large language model under low-bit weight-activation quantization. The computing device further comprises a graphics processing unit (GPU), a neural processing unit (NPU), or a tensor processing unit (TPU). The hardware interface module of the system is configured to load a low-bit model representation from the memory module and transmit the model representation to the GPU, NPU, or TPU for inference execution.

A neural processing device and a method for using shared page table thereof are provided. The neural processing device including at least one neural processor, a shared memory shared by the at least one neural processor, and a global interconnection configured to exchange data between the at least one neural processor and the shared memory, comprises at least one processing unit each of which included in each of the at least one neural processor and configured to provide logical addresses, a memory management unit configured to receive and translate the logical addresses into physical addresses, and a physical memory accessible by the physical addresses, wherein the memory management unit comprises a shared page table that has translation information between the logical addresses and the physical addresses and is shared by at least one process with each other.

A neural processing unit for performing inference operations of a large-scale language model based on an artificial neural network is disclosed. The neural processing unit according to the present disclosure includes a processing element core configured to perform an attention mechanism-based operation based on input data in vector format to output an operation result, a special function unit comprising a plurality of arithmetic circuits including at least one vector-dedicated arithmetic circuit that exclusively performs vector operations and at least one mixed arithmetic circuit capable of performing both vector and scalar operations, and configured to perform a special function operation on the operation result, and a controller configured to, upon receiving an RMS normalization operation execution command, activate at least one of the plurality of arithmetic circuits to control the special function unit to perform an operation of converting at least one of the operation result or the input data into a normalized vector whose magnitude is adjusted based on a root mean square (RMS), wherein the operation result may include an attention score for the input data.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

Disclosed is an electronic device comprising a neural processing unit (NPU), an RF circuit connected to at least one antenna, a modem for cellular communication, and a shared memory. The NPU may obtain, from the shared memory, time-sensitive input information and non-time-sensitive input information obtained from the modem and a sensor fusion module and stored in the shared memory, input the time-sensitive input information and the non-time-sensitive input information to a multi-modal deep learning algorithm and thereby generate output information for use in operating the RF circuit and the modem, and store the output information in the shared memory in order to make the RF circuit and the modem operate according to the output information.

The invention discloses a brain machine training system and method based on electroencephalogram attention assessment, and the system comprises an electroencephalogram data collection module which is used for collecting the electroencephalogram data and behavior data of a target user during the training period in real time, meanwhile, electroencephalogram data of the attention concentration state and the relaxation state of the target user within the preset duration are collected to serve as individual baseline data; the electroencephalogram data real-time processing module is used for analyzing the electroencephalogram data, and based on the analyzed electroencephalogram data and the individual baseline data, a standardized electroencephalogram attention score and neural processing efficiency are obtained through calculation; the data analysis and result visualization module is used for generating a behavior characteristic analysis report and an electroencephalogram attention analysis report of the target user; and the AI-based attention evaluation and suggestion module is used for generating an attention evaluation report according to a predefined report specification. And the practicability and the intelligent level of the brain-computer interface in cognitive training are improved.

Model level debugging of a machine learning design includes compiling the machine learning design for execution on target hardware using a compiler. Metadata for the machine is generated. The metadata specifies a mapping of buffers of the machine learning design to a plurality of memory levels of a memory architecture of the target hardware correlated with boundaries of the machine learning design. While running the machine learning design, debug data is dumped from the plurality of memory levels of the memory architecture based on the boundaries. The debug data is correlated with the boundaries of the machine learning design based on the metadata.

A signal processing device and a vehicle display device comprising same, according to one embodiment of the present disclosure, comprise: at least one neural processor; and a central processor for controlling the neural processor, wherein the central processor divides an artificial intelligence model to be executed in the neural processor into a plurality of groups and controls execution or suspension of the respective groups. Therefore, the neural processor can be efficiently operated.

Speech Recognition-Based Acoustic Analysis Instrument with Embedded Neural Processor

A firmware management operation. The firmware management operation includes providing an information handling system with a distributed unified BIOS; identifying a processor environment installed on an information handling system from a plurality of processor environments, the processor environment comprising a processor architecture; and, performing a cryptographic acceleration management operation, the cryptographic acceleration management operation accelerating performance of a cryptographic operation.

A neural network is able to reconfigure hardware accelerators on-the-fly without stopping downstream hardware accelerators. The neural network inserts a reconfiguration tag into the stream of feature data. If the reconfiguration tag matches an identification of a hardware accelerator, a reconfiguration process is initiated. Upstream hardware accelerators are paused while downstream hardware accelerators continue to operate. An epoch controller reconfigures the hardware accelerator via a bus. Normal operation of the neural network then resumes.

According to one example of the invention, a neural-like processing unit may include an array of processing elements for performing operations of a neural-like network model, and a post-processing unit configured to process data output from the array of processing elements. The post-processing unit includes a first computing circuit that extracts a subset of categories for each bounding box by comparing category scores of each category, and a second computing circuit that extracts one or more bounding boxes by comparing a category trust score of each bounding box to a threshold trust score.

According to the present disclosure, a device is provided. The device includes a first memory of a first capacity configured to store a first generative neural network model comprising a first parameters, and a first neural processing unit configured to generate a response corresponding to an input query utilizing the first generative neural network model stored in the first memory, and wherein the first neural processing unit may be configured to store a first execution code of the first generative neural network model compiled to process speculative decoding.

A neural processing unit (NPU) may perform computations in integer domains to execute a floating-point model. The NPU may include an input delivery unit (IDU), a processing engine, and a post-processing engine. The IDU may convert floating-point weights to integers, e.g., by normalizing the floating-point weights, mapping the normalized floating-point values to normalized integer values using a look-up table, and scaling up the normalized integer values into integer values. The IDU may load the integer values into the processing engine through an integer datapath in the NPU. The processing engine may compute an output tensor of a neural network operation using the integer values. The post-processing engine may perform per-channel quantization of the output tensor using channel-specific quantization parameters stored in configuration registers of the post-processing engine. The look-up table and configuration registers may be programmed with configuration parameters determined by a compiler.

Graphics processor (2) comprises a programmable execution unit (65) executing programs to perform graphics processing and a machine learning (ML) processing circuit (78) (e.g. neural processing accele

Systems and methods for exchanging synchronization information between various processing units using a synchronization network are disclosed. Systems and methods of the present disclosure include a device that includes a host and associated various neural processing units. Each neural processing unit can include a command communication module and a synchronization communication module. The command communication module can include circuitry for communicating with the host device over a host network. The synchronization communication module can include circuitry that enables communication between the various neural processing units over a synchronization network. The various neural processing units can be configured to obtain a synchronized update of a machine learning model by each neural processing unit. The synchronized update can be obtained at least in part by exchanging synchronization information using the synchronization network. Each neural processing unit can maintain a version of the machine learning model and can synchronize the version using the synchronized update.

A neural processing device and method for pruning thereof are provided. The neural processing device includes a processing unit configured to perform calculations, an L0 memory configured to store input and output data of the processing unit, wherein the input and output data include a two-dimensional weight matrix and a weight manipulator configured to receive the two-dimensional weight matrix and partition it into preset sizes to thereby generate partitioned matrices, to generate a pruning matrix by pruning the partitioned matrix, and to transmit the pruning matrix to the processing unit.

According to one example of the present disclosure, a post-processing unit may be provided. The post-processing unit may be implemented in register transfer level (RTL) code and designed to interface with a neural processing unit (NPU) configured for object detection computations of a neural network model. The post-processing unit may include a processing unit configured to filter a plurality of bounding boxes transmitted from the NPU and output only those that satisfy a particular condition and one or more input registers configured to store data output from the processing unit.

Embodiments relate to streaming operations in a neural processor circuit that includes a neural engine circuit and a data processor circuit. The neural engine circuit performs first operations on a first input tensor of a first layer to generate a first output tensor, and second operations on a second input tensor of a second layer at a higher hierarchy than the first layer, the second input tensor corresponding to the first output tensor. The data processor circuit stores a portion of the first input tensor for access by the neural engine circuit to perform a subset of the first operations and generate a portion of the first output tensor. The data processor circuit stores the portion of the first output tensor for access by the neural engine circuit as a portion of the second input tensor to perform a subset of the second operations.

The invention discloses a temperature monitoring system and method and a substrate management controller, and relates to the technical field of computers, an analog-to-digital conversion module directly collects voltage signals at the two ends of a sampling resistor arranged in a power supply loop, and the problems of interface complexity and signal interference caused by distributed wiring of temperature sensors are solved; and the neural processing module performs analysis and feature extraction on historical time sequence data of the sampling voltage signal by using a pre-trained time sequence reasoning model, can adaptively learn a nonlinear resistance value change rule caused by heating in long-term operation of the sampling resistor, and realizes dynamic correction and calculation on the actual temperature. The technical problems that temperature collection depends on a large number of entity sensors, wiring is complex, cost is high and temperature calculation precision is insufficient are solved, and the technical effects that on the premise that additional temperature sensors do not need to be added, the component temperature is monitored, hardware design complexity and cost are reduced, and temperature monitoring reliability and stability are improved are achieved.

An image processing method includes receiving an image including an object; classifying at least one object in the image using a first model on the basis of an artificial neural network configured to classify the at least one object by inputting the image; and obtaining an image having improved quality according to the at least one object by inputting the image in which the at least one object is classified by using at least one model among a plurality of second models on the basis of an artificial neural network configured to output a specialized processing applied image according to a particular object by inputting the received image.