22 results about "Neuromorphic circuits" patented technology

An analog neuromorphic circuit is disclosed having a first and a second memristor crossbar configuration implemented into an autoencoder. The first memristor crossbar configuration includes resistive memories that provide resistance values to each corresponding input voltage applied to the first memristor crossbar configuration to generate first output voltages that are compressed from the input voltages. The second memristor crossbar includes resistive memories that provide resistance values to each corresponding first output voltage applied to the second memristor crossbar configuration to generate second output voltages that are decompressed from the first output voltages. A controller compares the second output voltages to the input voltages to determine if the second output voltages are within a threshold of the input voltages. The controller generates an alert when the second output voltages exceed the threshold from the input voltages thereby indicating that input data associated with the input voltages has not been previously identified.

This solution addresses the challenges of reduced learning accuracy and reproducibility in the integration of short-term plasticity (STP) and long-term plasticity (LTP) at the single-element level, due to adjacent element interference and difficulties in non-destructive readout. [Solution] This system utilizes a neuromorphic circuit array based on single elements capable of expressing STP and LTP, and reduces adjacent element interference through interference suppression circuits and common electrode control. The internal state of a single element can be read non-destructively, enabling STP→LTP transitions and spike timing-dependent plasticity (STDP) control according to input pulse conditions. This enables stable and highly reproducible learning operations even in large-scale arrays, improving neuromorphic computation performance.

The application provides a gate-regulated lateral neuromorphic device doped with an ionic salt and a preparation method thereof.The whole device comprises a substrate, an electrolyte functional layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate and source-drain electrodes, the electrolyte functional layer is arranged on the substrate, the charge trapping layer is arranged on the side of the electrolyte functional layer away from the substrate, and the organic semiconductor layer is arranged on the side of the charge trapping layer away from the electrolyte functional layer; the organic semiconductor layer is separated, and the horizontal gate and the source-drain electrodes are arranged above the organic semiconductor layer respectively, the semiconductor below the source-drain electrodes serves as a channel layer, and the semiconductor below the horizontal gate serves as a floating gate layer.The neuromorphic device has good electrical performance, has higher stability in an air environment compared with a hydrogen ion electrolyte device, and has a significant light response and a clear hysteresis phenomenon under the action of a negative gate voltage.The device has simple process and low cost, and can be widely applied in neuromorphic circuits.

Neuromorphic circuit structure (100), comprising: a first vertically extending neural node (102A) configured to generate an output signal based on at least one input to the first vertically extending neural node (102A); a connection stack (104) adjacent to the vertically extending neural node (102A), wherein the connection stack (104) includes a first conductor (106) coupled to the first vertically extending neural node (120A) and configured to receive the output signal, wherein a second conductor (108) is vertically separated from the first conductor (106), and wherein a memory via (114) vertically couples the first conductor (106) to the second conductor (108); and a second vertically extending neural node (102B) next to the connection stack (104), wherein the second vertically extending neural node (102B) is coupled to the second conductor (108) for receiving the output signal from the first vertically extending neural node (102A).

An apparatus, wherein the apparatus comprises: a single photon avalanche diode sensor comprising a plurality of single photon avalanche diode pixels, each single photon avalanche diode pixel configured to generate and output a light detection event to a neuromorphic circuit; and a neuromorphic circuit implementing a plurality of spiking neurons, wherein the neuromorphic circuit is configured to process the light detection events using the plurality of spiking neurons.

A spiking neuromorphic circuit that instantiates a finite element methods (FEM) mesh is provided. The circuit comprises a number of groups of spiking neurons, wherein each group of spiking neurons represents a mesh node in the FEM mesh, wherein the FEM mesh represents a linear system. A bias current represents conditions in the linear system. Interaction weights between adjacent mesh nodes are proportional to the linear system represented by the FEM mesh. The spiking neurons within each group of spiking neurons spike in a manner that flows to a solution variable for the respective mesh node.

A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.

The present invention concerns a neuromorphic circuit (10) implementing an oscillatory neural network, the neuromorphic circuit (10) comprising : - neuron units (12), each neuron unit (12) being an analog oscillator adapted to convert an incoming analog signal having a specific waveform on an analog input (12I) of the neuron unit (12) into a digital output signal, and - synapse units (14), each synapse unit (14) being adapted to multiply a digital output from a neuron unit (12) with a respective synaptic weight to output a weighted signal sent to the analog input (12I) of a neuron unit (12).

An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

A neuromorphic circuit (500) includes a crossbar synapse array unit. The crossbar synapse array unit includes a complementary metal oxide semiconductor (CMOS) transistor (T6), the on-resistance of which is controlled by the gate voltage of the CMOS transistor (T6) to update the weight of the crossbar synapse array unit. The neuromorphic circuit (500) also includes a set of row lines, each of which connects the synapse array unit in series with a plurality of presynaptic neurons at a first end of the synapse array unit. The neuromorphic circuit (500) also includes a set of column lines, each of which connects the synapse array unit in series with a plurality of postsynaptic neurons at a second end of the synapse array unit. The gate voltage of the CMOS transistor (T6) is controlled by performing a charge sharing technique, wherein the charge sharing technique uses non-overlapping pulses on a cell control line aligned with the set of row lines and the set of column lines to update the weight of the crossbar synapse array unit.

An analog neuromorphic circuit is discloses input voltages applied to inputs of the analog neuromorphic circuit. Resistor banks that include fixed resistors provide a variable resistance to each input voltage. The variable resistance of each resistor bank is based on an overall resistance value of fixed resistors included in each resistor bank. A controller adjusts the variable resistance of each resistor bank by adjusting the overall resistance value of the fixed resistors to obtain a functionality of the analog neuromorphic circuit.. The overall resistance value of each resistor bank is generated from a fixed resistance value of each fixed resistor relative to each other as included in the resistor bank. The controller executes the functionality of the analog neuromorphic circuit from the input voltages multiplied in parallel with corresponding currents of the input voltages added in parallel and the adjusted variable resistance of each resistor bank.

The present invention concerns a neuromorphic circuit (10) implementing an oscillatory neural network, the neuromorphic circuit (10) comprising : - neuron units (12), each neuron unit (12) being an analog oscillator adapted to convert an incoming analog signal having a specific waveform on an analog input (12I) of the neuron unit (12) into a digital output signal, and - synapse units (14), each synapse unit (14) being adapted to multiply a digital output from a neuron unit (12) with a respective synaptic weight to output a weighted signal sent to the analog input (12I) of a neuron unit (12).

Provided is a neuromorphic circuit including an input module configured to generate an input voltage, an output module configured to measure a current transmitted from the input module and generate an output voltage, synapse modules configured to electrically connect the input module and the output module and determine a current to be transmitted to the output module and including a memory element to which a weight is assigned, and a crossing module configured to control a direction of current flowing through the synapse modules.

A neuromorphic circuit suitable for implementing a neural network includes word lines, pairs of complementary bit-lines, source lines, a set of elementary cells, and an electronic circuit implementing a neurone having an output. The electronic circuit includes a set of logic components, a counting unit, and a comparison unit having a comparator and a comparison voltage generator, the comparator being configured to compare the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit.

A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source / drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source / drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and / or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program / erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

An update unit, a neuromorphic circuit including the same, and a method of operating the neuromorphic circuit are disclosed. The disclosed neuromorphic circuit may include an update cell array, which may include: a plurality of word lines; a plurality of bit lines crossing the plurality of word lines; and a plurality of update units disposed at a plurality of intersections of the plurality of word lines and the plurality of bit lines, respectively, the update units may include: a capacitor including a first electrode and a second electrode; a switching transistor including a first node connected to the second electrode, a second node connected to the bit line, and a gate connected to the word line; and a charge / discharge circuit unit connected to the capacitor and configured to charge and discharge the capacitor. A comparison circuit section connected to each of the plurality of bit lines may also be provided, and the comparison circuit section may be configured to output a first signal, a second signal, and a third signal separately based on a positive (+) threshold voltage and a negative (-) threshold voltage.

A direction-selective neuromorphic circuit is provided comprising a first dendrite comprising first and second compartments and a destination compartment arranged sequentially, wherein the first dendrite is tuned to detect a first pattern. A second dendrite comprises first and second compartments and a destination compartment arranged sequentially, wherein the second dendrite is tuned to detect a second pattern. Input from a first spike generator is input to the first compartment of the first dendrite and the second compartment of the second dendrite. Input from a second spike generator is input to the first compartment of the second dendrite and the second compartment of the first dendrite. Responsive to detecting the first pattern, the destination compartment of the first dendrite spikes and laterally inhibits the second dendrite. Responsive to detecting the second pattern, the destination compartment of the second dendrite spikes and laterally inhibits the first dendrite.

An update cell, a neuromorphic circuit including the same, and a method of operating a neuromorphic circuit are disclosed. The disclosed neuromorphic circuit may include an update cell array, wherein the update cell array may include a plurality of word lines, a plurality of bit lines which intersect the plurality of word lines, and a plurality of update cells respectively disposed at intersections of the plurality of word lines and the plurality of bit lines. The update cell may include a capacitor including a first electrode and a second electrode, a switching transistor including a first node connected to the second electrode, a second node connected to the bit line, and a gate connected to the word line, and a charging / discharging circuit unit connected to the capacitor for charging and discharging the capacitor. A comparison circuit connected to each of the plurality of bit lines may be further provided, and the comparison circuit may be configured to distinguish and output a first signal, a second signal, and a third signal based on a positive (+) threshold voltage and a negative (-) threshold voltage.

A method of shunting inhibition mechanism in a neuromorphic circuit is provided. The method comprises inputting excitatory signals to an artificial neuron soma having a resting membrane potential. Shunting conductances are input to the artificial neuron soma to multiply response to the excitatory signals in the artificial neuron soma, wherein the shunting conductances have a reversal potential approximately equal to the resting membrane potential of the artificial neuron, and wherein increasing the shunting conductances increases membrane conductance of the artificial neuron soma.

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.