13 results about "Neuromorphic circuits" patented technology

This solution addresses the challenges of reduced learning accuracy and reproducibility in the integration of short-term plasticity (STP) and long-term plasticity (LTP) at the single-element level, due to adjacent element interference and difficulties in non-destructive readout. [Solution] This system utilizes a neuromorphic circuit array based on single elements capable of expressing STP and LTP, and reduces adjacent element interference through interference suppression circuits and common electrode control. The internal state of a single element can be read non-destructively, enabling STP→LTP transitions and spike timing-dependent plasticity (STDP) control according to input pulse conditions. This enables stable and highly reproducible learning operations even in large-scale arrays, improving neuromorphic computation performance.

The application provides a gate-regulated lateral neuromorphic device doped with an ionic salt and a preparation method thereof.The whole device comprises a substrate, an electrolyte functional layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate and source-drain electrodes, the electrolyte functional layer is arranged on the substrate, the charge trapping layer is arranged on the side of the electrolyte functional layer away from the substrate, and the organic semiconductor layer is arranged on the side of the charge trapping layer away from the electrolyte functional layer; the organic semiconductor layer is separated, and the horizontal gate and the source-drain electrodes are arranged above the organic semiconductor layer respectively, the semiconductor below the source-drain electrodes serves as a channel layer, and the semiconductor below the horizontal gate serves as a floating gate layer.The neuromorphic device has good electrical performance, has higher stability in an air environment compared with a hydrogen ion electrolyte device, and has a significant light response and a clear hysteresis phenomenon under the action of a negative gate voltage.The device has simple process and low cost, and can be widely applied in neuromorphic circuits.

Neuromorphic circuit structure (100), comprising: a first vertically extending neural node (102A) configured to generate an output signal based on at least one input to the first vertically extending neural node (102A); a connection stack (104) adjacent to the vertically extending neural node (102A), wherein the connection stack (104) includes a first conductor (106) coupled to the first vertically extending neural node (120A) and configured to receive the output signal, wherein a second conductor (108) is vertically separated from the first conductor (106), and wherein a memory via (114) vertically couples the first conductor (106) to the second conductor (108); and a second vertically extending neural node (102B) next to the connection stack (104), wherein the second vertically extending neural node (102B) is coupled to the second conductor (108) for receiving the output signal from the first vertically extending neural node (102A).

An apparatus, wherein the apparatus comprises: a single photon avalanche diode sensor comprising a plurality of single photon avalanche diode pixels, each single photon avalanche diode pixel configured to generate and output a light detection event to a neuromorphic circuit; and a neuromorphic circuit implementing a plurality of spiking neurons, wherein the neuromorphic circuit is configured to process the light detection events using the plurality of spiking neurons.

A spiking neuromorphic circuit that instantiates a finite element methods (FEM) mesh is provided. The circuit comprises a number of groups of spiking neurons, wherein each group of spiking neurons represents a mesh node in the FEM mesh, wherein the FEM mesh represents a linear system. A bias current represents conditions in the linear system. Interaction weights between adjacent mesh nodes are proportional to the linear system represented by the FEM mesh. The spiking neurons within each group of spiking neurons spike in a manner that flows to a solution variable for the respective mesh node.

The present invention concerns a neuromorphic circuit (10) implementing an oscillatory neural network, the neuromorphic circuit (10) comprising : - neuron units (12), each neuron unit (12) being an analog oscillator adapted to convert an incoming analog signal having a specific waveform on an analog input (12I) of the neuron unit (12) into a digital output signal, and - synapse units (14), each synapse unit (14) being adapted to multiply a digital output from a neuron unit (12) with a respective synaptic weight to output a weighted signal sent to the analog input (12I) of a neuron unit (12).

The present invention concerns a neuromorphic circuit (10) implementing an oscillatory neural network, the neuromorphic circuit (10) comprising : - neuron units (12), each neuron unit (12) being an analog oscillator adapted to convert an incoming analog signal having a specific waveform on an analog input (12I) of the neuron unit (12) into a digital output signal, and - synapse units (14), each synapse unit (14) being adapted to multiply a digital output from a neuron unit (12) with a respective synaptic weight to output a weighted signal sent to the analog input (12I) of a neuron unit (12).

A neuromorphic circuit suitable for implementing a neural network includes word lines, pairs of complementary bit-lines, source lines, a set of elementary cells, and an electronic circuit implementing a neurone having an output. The electronic circuit includes a set of logic components, a counting unit, and a comparison unit having a comparator and a comparison voltage generator, the comparator being configured to compare the output of the counting unit with the comparison voltage generated by the comparison voltage generator in order to output a signal dependent on the comparison and corresponding to the output of the electronic circuit.

A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source / drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source / drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and / or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program / erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.

A direction-selective neuromorphic circuit is provided comprising a first dendrite comprising first and second compartments and a destination compartment arranged sequentially, wherein the first dendrite is tuned to detect a first pattern. A second dendrite comprises first and second compartments and a destination compartment arranged sequentially, wherein the second dendrite is tuned to detect a second pattern. Input from a first spike generator is input to the first compartment of the first dendrite and the second compartment of the second dendrite. Input from a second spike generator is input to the first compartment of the second dendrite and the second compartment of the first dendrite. Responsive to detecting the first pattern, the destination compartment of the first dendrite spikes and laterally inhibits the second dendrite. Responsive to detecting the second pattern, the destination compartment of the second dendrite spikes and laterally inhibits the first dendrite.

A method of shunting inhibition mechanism in a neuromorphic circuit is provided. The method comprises inputting excitatory signals to an artificial neuron soma having a resting membrane potential. Shunting conductances are input to the artificial neuron soma to multiply response to the excitatory signals in the artificial neuron soma, wherein the shunting conductances have a reversal potential approximately equal to the resting membrane potential of the artificial neuron, and wherein increasing the shunting conductances increases membrane conductance of the artificial neuron soma.

An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.