Transistorless all-memristor neuromorphic circuits for in-memory computing

Abstract

A circuit for multiplying a number N of first operands each by a corresponding second operand, and for adding the products of the multiplications, with N≥2; the circuit comprising: N input conductors; N programmable conductance circuits connected each between one of the input conductors and at least one output conductor; each programmable conductance circuit being arranged to be programmable at a value depending in a known manner from one of the first operands; each input conductor being arranged to receive from an input circuit an input train of voltage spikes having a spike rate that derives in a known manner from one of the second operands; and at least one output circuit arranged to generate an output train of voltage spikes having a spike rate that derives in a known manner from a sum over time of the spikes received on the at least one output conductor.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is related to and claims priority from U.S. Provisional Application Ser. No. 62 / 844,611, filed May 7, 2019. This application is related to and claims priority from U.S. Provisional Application Ser. No. 62 / 860,915, filed Jun. 13, 2019. This application is related to U.S. Non-Provisional Application (NP 632100 in prep), which is incorporated by reference herein as though set forth in full.STATEMENT REGARDING FEDERAL FUNDING[0002]This invention was made under U.S. Government contract FA8650-18-C-7869. The U.S. Government has certain rights in this invention.FIELD OF THE INVENTION[0003]Embodiments of the present technology relate generally to a device and method to conduct fast and energy-efficient Multiply-ACcumulate (MAC) arithmetic operations; in particular Vector-Matrix Multiplication (VMM) operations in a parallel fashion.BACKGROUND[0004]One way to implement VMM operations in hardware is an architecture known as a crossb...

AI Technical Summary

Benefits of technology

[0045]concept 29. The neuromorphic crossbar array circuit of concept 24, wherein each excitatory tonic neuron circuit comprises first and second negative differential resistance devices biased each with opposite polarities, said first and second negative differential resistance devices being coupled to first and second grounded capacitors.

[0046]Concept 30. The neuromorphic crossbar array circuit of concept 29, wherein: said first negative differential resistance device has a first node connected to an input node of the excitatory tonic neuron circuit by a first load resistor and a second node connected to a

Problems solved by technology

Although hybrid CMOS-memristor dot-product accelerators such as illustrated in FIG. 1B can realize analog domain computation in a parallel fashion, they face several challenges.

One challenge is that the interfacing/communication with the external digital circuitries necessitate

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