81results about "Resistors" patented technology

A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

An apparatus includes a resistor structure within a back end of line (BEOL) via level. The resistor structure includes a lower resistor film, a first insulating layer over the lower resistor film, an upper resistor film over the first insulating layer, and a second insulating layer over the upper resistor film. First and second upper metal lines are above the second insulating layer, a first end of the upper resistor film is coupled to the first upper metal line by a first upper via or contact, and a second end of the upper resistor film is coupled to the second upper metal line by a second upper via or contact. The apparatus may be a resistor or a thermistor of a semiconductor device.

A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

A test key configured to measure resistance of a through semiconductor via in a semiconductor substrate is provided. The test key includes a first resistor, a first conductor, a first probe pad, a second conductor, a second probe pad, a third conductor, a third probe pad, a fourth conductor, and a fourth probe pad. The first probe pad is electrically connected to a first end of the through semiconductor via by the first resistor and the first conductor. The second probe pad is electrically connected to the first end of the through semiconductor via by the second conductor. The third probe pad is electrically connected to a second end of the through semiconductor via by the third conductor. The fourth probe pad is electrically connected to the second end of the through semiconductor via by the fourth conductor.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes first and second gate dielectric layers over a fin. First and second gate electrodes are over the first and second gate dielectric layers, respectively, the first and second gate electrodes both having an insulating cap having a top surface. First dielectric spacer are adjacent the first side of the first gate electrode. A trench contact structure is over a semiconductor source or drain region adjacent first and second dielectric spacers, the trench contact structure comprising an insulating cap on a conductive structure, the insulating cap of the trench contact structure having a top surface substantially co-planar with the insulating caps of the first and second gate electrodes.

To provide a circuit element that can improve its characteristics.SOLUTION: According to an embodiment, a circuit element includes a first conductive member, a second conductive member, a first layer, and a dielectric film. The first layer is between the first conductive layer and the second conductive layer. The first layer includes a first structure and a plurality of second structures. The plurality of second structures are arranged side by side on a first plane intersecting a first direction from the first conductive member to the second conductive member. At least part of the first structure is between the plurality of second structures on the first plane. A second conductivity of the plurality of second structures is different from a first conductivity of the first structure. The first layer is electrically connected to the second conductive member. The dielectric film is between the first conductive member and the first layer.SELECTED DRAWING: Figure 1

In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way.

A semiconductor device includes a first dielectric film, a resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element contains silicon, chromium, and carbon. The silicon concentration in the resistor element increases from a center part of the resistor element towards an upper surface of the resistor element, and also increases from the center part of the resistor element towards a lower surface of the resistor element.

A refrigeration device (90) comprises housings (105; 205), a refrigerant circuit (60), power supply units (45; 46), grounding lines (51; 95), and grounding resistors (55; 94). The refrigerant circuit (60) circulates a refrigerant (65) that can cause a disproportionation reaction. The power supply units (45; 46) receive power from a commercial power supply (47). The grounding lines (51; 95) electrically connect the housings (105; 205) to an external grounding surface (G). The grounding resistors (55; 94) are electrically connected to the grounding lines (51; 95) and have a resistance value of 0.1Ω or greater.

According to one embodiment, a semiconductor device includes a substrate having a first surface and an insulator that surrounds a first region of the first surface. A gate electrode is on the first region and has a first resistivity. A first conductor is also on the first region. The first conductor comprises a same material as the gate electrode, but has a second resistivity that is different from the first resistivity. The resistivity may be different, for example, by either use of different dopants / impurities or different concentrations of dopants / impurities. Resistivity may also be different due to inclusion of a metal silicide on the conductors or not.

An electric braking resistor-based heat generator for process fluids or emulsions includes a housing having a connection end, a body portion, and a closed end, where at least part of the housing forms an at least partially enclosed portion, an electric braking resistor at least partially disposed within the enclosed portion of the housing, and a thermally conductive material disposed within the enclosed portion of the housing that provides thermal communication between the electric braking resistor and the housing. The electric braking resistor converts electrical energy provided by an electric power source into thermal energy that is thermally communicated from the housing to the process fluids or emulsions.

In a DC-DC converter (200'), a layout is designed to enable utilization of the conductive trace connecting the converter output node (N2) to an output bump (BB1, BB2) at which the load (RL, CL) is attached as a sense resistor (Rs). The layout forces the output current down into lower metallization levels (201) of an interconnect layer reaching the converter output node (N2) before the output current flows up into this conductive trace (212) and out through the output bump (BB1, BB2). The conductive trace (212) includes resistive pillars connected in parallel or series between the lower metallization levels (201) and a top metallization layer (207c) of the conductive trace (212), with these resistive pillars being substantially greater in resistance than the lower metallization levels (201) and the top metallization layer (207c) of the conductive trace (212).

The present invention realizes a printed circuit board and a power conversion device which are capable of preventing short circuit or insulation failure between fuse terminals after a fuse blowout due to overcurrent or the like at the time of an abnormality. A printed circuit board (10) comprises: a substrate (2) having a through-hole (3a); and a fuse (1) disposed on the substrate (2) so as to face the through-hole (3a) and attached by means of connection terminals (1b). The fuse (1) is provided so that a space (8) is formed at a distance from the substrate (2).

In a DC-DC converter, a layout is designed to enable utilization the conductive trace connecting the converter output node to an output bump at which the load is attached as a sense resistor. The layout forces the output current down into lower metallization levels of an interconnect layer reaching the converter output node before the output current flows up into this conductive trace and out through the output bump. The conductive trace includes resistive pillars connected in parallel or series between the lower metallization levels and a top metallization layer of the conductive trace, with these resistive pillars being substantially greater in resistance than the lower metallization levels and the top metallization layer of the conductive trace.

To discharge a smoothing capacitor in a shorter time and maintain temperature of a resistance element at heat-resistant temperature or lower in a discharge circuit of a smoothing capacitor.SOLUTION: A discharge circuit (40) causes a smoothing capacitor for smoothing a DC voltage to discharge through a plurality of resistance elements (41) mounted on a substrate (50). The discharge circuit includes a series connection body in which at least three resistance elements (41 (11 to 15)) arranged at intervals in a first direction (X1) are connected in series by wires (47 (11 to 14)). A resistance value of the resistance element included in the series connection body becomes smaller as the resistance element is closer to a center in the first direction. The resistor elements adjacent to each other in the first direction included in the series-connection body are located at different positions in a second direction (X2) perpendicular to the first direction.SELECTED DRAWING: Figure 4

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

In a DC-DC converter (200'), a layout is designed to enable utilization of the conductive trace connecting the converter output node (N2) to an output bump (BB1, BB2) at which the load (RL, CL) is attached as a sense resistor (Rs). The layout forces the output current down into lower metallization levels (201) of an interconnect layer reaching the converter output node (N2) before the output current flows up into this conductive trace (212) and out through the output bump (BB1, BB2). The conductive trace (212) includes resistive pillars connected in parallel or series between the lower metallization levels (201) and a top metallization layer (207c) of the conductive trace (212), with these resistive pillars being substantially greater in resistance than the lower metallization levels (201) and the top metallization layer (207c) of the conductive trace (212).

Provided are an electronic element in which a physical quantity of a passive element can be varied in a wide range including the case where the physical quantity is 0(zero), and a circuit device. A variable capacitance element (100) comprises a switch portion (10) and an element portion (20) constituting a capacitor. The switch portion (10) includes a source electrode (5), a drain electrode (6), a channel forming film (4) formed overlapping with at least a part of the source electrode (5) and at least a part of the drain electrode (6), a gate insulating film (3) formed overlapping with the channel forming film (4), and a gate electrode (2) formed on the gate insulating film (3). The element portion (20) includes a terminal electrode (5a) (first terminal electrode) electrically connected to the source electrode (5), and a terminal electrode (22) (second terminal electrode) that sandwiches the dielectric layer (3a) or adjoins the dielectric layer (3a), and that constitutes a capacitor between a part (electrode 6c) of the drain electrode (6) and the terminal electrode (22). The dielectric layer and the gate insulating film are of the same insulating film.

Various embodiments of the present disclosure are directed towards an integrated chip including a thin film resistor (TFR) layer overlying a semiconductor substrate. A first conductive structure is disposed on an outer region of the TFR layer. The first conductive structure comprises a lateral portion adjacent to a vertical portion. A height of the vertical portion is greater than a height of the lateral portion. A capping structure is disposed on a middle region of the TFR layer and abuts the vertical portion of the first conductive structure.

A semiconductor device includes a capacitor and a resistor. The capacitor includes a first plate, a capacitor dielectric layer disposed over the first plate, and a second plate disposed over the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor, formed of a same conductive material, are defined in a single patterning process.

Disclosed is a fan-out package in which two or more dies are integrated in a fan-out packaging process, wherein the fan-out package includes a bridge structure including a bridge substrate formed on one side of the fan-out package, a redistribution layer formed on the bridge substrate, the redistribution layer including at least one trace, the redistribution layer being configured to electrically connect the dies to each other, and a passive element formed in the redistribution layer by patterning. The routing density of the trace is relieved, and electrical performance is improved by the provision of the passive element.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

The utility model relates to the technical field of resistors, in particular to a high-power small-structure resistor structure. The resistor comprises a square ceramic shell, a resistor module arranged in the square ceramic shell, and a quartz sand mixed filler which is filled in the square ceramic shell and covers the resistor module, the resistor module comprises a fuse block arranged in the middle and a plurality of resistor blocks which are respectively arranged on the periphery of the fuse block and are arranged by taking the fuse block as the center, and the resistor blocks are sequentially arranged clockwise by taking the fuse block as the center and are connected in series. The beneficial effects of the utility model are that according to the technical scheme, the resistors are annularly arranged by taking the fuse block as the center, and then the resistors are sequentially connected in series through a special connection mode, so that an integral strip-shaped structure is formed, the structure is minimized, the space utilization is maximized, high power is provided for cooperative use, and the impact resistance of the product in a circuit is improved.

A method of manufacturing a resistor-transistor-logic circuit with GaN structures, including steps of forming a GaN layer, an AlGaN barrier layer and a p-type doped GaN capping layer on a substrate, patterning the p-type doped GaN capping layer into multiple p-type doped GaN capping patterns, wherein the GaN layer under parts of the p-type doped GaN capping patterns is converted into gate depletion regions, and the GaN layer not covered by the p-type doped GaN capping patterns in a resistor region functions as 2DEG resistors, forming a passivation layer on the GaN layer and the p-type doped GaN capping patterns, forming multiple sources and drains on the GaN layer, and forming multiple gates on the p-type doped GaN capping patterns, wherein the gates, sources and drains in a high-voltage device region constitute high-voltage HEMTs, and the gates, sources and drains in a low-voltage device region constitute low-voltage logic FETs.

Semiconductor structures having low resistance via contacts and methods of fabricating the same are provided. An example semiconductor structure includes a substrate, a dielectric layer disposed over the substrate, a resistor disposed in the dielectric layer, and a resistor via contact disposed in the dielectric layer the resistor. The resistor via contact further includes a first layer disposed on and in contact with the resistor, a second layer disposed on the first layer, and a third layer disposed on the second layer. The first layer has a first thickness and includes a first material having a first resistivity, the second layer has a second thickness and includes a second material, and the third layer has a third thickness and includes a third material having a second resistivity. The first thickness is more than the third thickness, and the first resistivity is less than the second resistivity.

The present invention provides a copper alloy material that suppresses fluctuations in the temperature coefficient of resistance (TCR) and exhibits good solder wettability and molten alloy flowability, a resistor containing the copper alloy material, and a resistor equipped with the resistor. [Solution] A copper alloy material for resistance, comprising Mn: 10.0% by mass or more and 14.0% by mass or less, Ni: 1.0% by mass or more and 4.0% by mass or less, and Al: 0.3% by mass or more and less than 1.0% by mass, with the remainder being Cu and unavoidable impurities.

A refrigeration device (90) is provided with housings (105, 205), a refrigerant circuit (60), power supply units (45, 46), ground wires (51, 95), and ground resistors (55, 94). The refrigerant circuit (60) circulates a refrigerant (65) capable of generating a disproportionation reaction. Power supply units (45, 46) receive power from a commercial power supply (47). Ground wires (51, 95) conduct the housings (105, 205) and an external ground (G). The ground resistors (55, 94) are electrically connected to the ground wires (51, 95), and have a resistance value of 0.1 Omega or more.

A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate thereby defining an active region and a passive region in the semiconductor substrate and spaced apart from each other by the STI region, forming a first sacrificial gate structure over the active region and a second sacrificial gate structure over the passive region, forming first source / drain regions in the active region and second source / drain regions in the passive region, after forming the first and second source / drain regions, replacing the first sacrificial gate structure with a metal gate structure and the second sacrificial gate structure with a metal resistor structure, the metal resistor structure corresponding to a dummy gate, forming a first gate contact over the metal gate structure, and a pair of resistor contacts over the metal resistor structure, and electrically coupling a set of metal lines with the metal resistor structure by the pair of resistor contacts.

Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.

The semiconductor device includes a multi-finger high electron mobility transistor (HEMT). The multi-finger HEMT includes a two-dimensional electron gas (2-DEG); a plurality of source fingers, wherein a first source finger of the plurality of source fingers extends continuously across the 2-DEG, and a second source finger of the plurality of source fingers is discontinuous across the 2-DEG; and a plurality of drain fingers, wherein the plurality of drain fingers is interdigitated with the plurality of source fingers. The second source finger is part of a current sensing element.