48 results about "Process variability" patented technology

A method and on-chip controller for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability / variability controller arrangement for implementing the inventive method.

A method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an arrangement for implementing the inventive method.

In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability / variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

A method for forecasting batch end conditions through their depiction as a multi-dimensional regions of uncertainty is disclosed. A visualization of the current condition of a continuous process and visualization of the simulated effect of user control moves are generated for a user. Volume visualization tools for viewing and querying intersecting solids in 3-dimensional space are utilized to perform the process visualization. Interactive tools for slicing multi-dimensional (>3) regions and drawing superimposed projections in 3-D space are provided. Additionally, graphical manipulation of the views of process conditions is accomplished by changing the hypothetical future values of contributing variables online in order to provide users the ability to simulate the effect of proposed control actions. The illustrative embodiment of the present invention may also be utilized in combination with a graphical programming environment supporting the execution and simulation of block diagrams and correspondingly generated process data. The scores representing the process condition may depend on estimated physical quantities as well as representations of process variability.

Processing test results from a plurality of individual semiconductor testers by analyzing each test result at an adaptive test engine. A centralized system jointly analyzes all the test results from the plurality of individual semiconductor testers. The adaptive test engine or the centralized system identifies, based on the analysis of each test result or the joint analysis of all the test results, one or more of: a test environmental issue, a tester variability issue, a tester calibration issue, a product variability issue, and a manufacturing process variability issue. The adaptive test engine or the centralized system determines whether one or more of the plurality of individual semiconductor testers causes one or more of the identified issues or whether semiconductor products tested by the plurality of individual semiconductor testers causes one or more of the identified issues.

An improved automatic feedback control scheme enhances plasma spraying of powdered material through reduction of process variability and providing better ability to engineer coating structure. The present inventors discovered that controlling centroid position of the spatial distribution along with other output parameters, such as particle temperature, particle velocity, and molten mass flux rate, vastly increases control over the sprayed coating structure, including vertical and horizontal cracks, voids, and porosity. It also allows improved control over graded layers or compositionally varying layers of material, reduces variations, including variation in coating thickness, and allows increasing deposition rate. Various measurement and system control schemes are provided.

A real time alarm classification system and method of use and, more particularly, to a residual gas analyzer configured to identify specific root causes of an abnormal condition such as, for example, contamination, undesirable process variability and equipment malfunction in wafer processing. The real-time alarm classification system comprises a computer infrastructure operable to: generate top contributors associated with an alarm triggered by sensed abnormal conditions; compare the top contributors to contributors of historic RGA (residual gas analyzer) alarms of known root causes that were generated by a validated model; and provide a probable root cause of the sensed abnormal conditions when a match is found between the top contributors and the contributors associated with the historic RGA alarms of known root causes. A method and computer readable medium is also contemplated to provide the processes.

A system and method are provided for a PTAT cell with no resistors which can operate at low power, has less sensitivity to process variation, occupies less silicon area, and has low noise. Further, a system and method are provided to scale up the reference voltage and current through a cascade of unit cells. Still further, a system and method are provided for PTAT component to be fine-tuned, advantageously providing less process variability and less temperature sensitivity.

A method for forecasting batch end conditions through their depiction as a multi-dimensional regions of uncertainty is disclosed. A visualization of the current condition of a continuous process and visualization of the simulated effect of user control moves are generated for a user. Volume visualization tools for viewing and querying intersecting solids in 3-dimensional space are utilized to perform the process visualization. Interactive tools for slicing multi-dimensional (>3) regions and drawing superimposed projections in 3-D space are provided. Additionally, graphical manipulation of the views of process conditions is accomplished by changing the hypothetical future values of contributing variables online in order to provide users the ability to simulate the effect of proposed control actions. The illustrative embodiment of the present invention may also be utilized in combination with a graphical programming environment supporting the execution and simulation of block diagrams and correspondingly generated process data. The scores representing the process condition may depend on estimated physical quantities as well as representations of process variability.

A method of producing a fermentation-based product, such as ethanol, comprises fermenting a sugar-containing medium with yeast in the presence of an aliphatic or aromatic monoaldehyde or dialdehyde, a formaldehyde-releasing compound, or a combination thereof, in an amount sufficient to reduce or control a bacterial population in the sugar-containing medium. The additive may enable reduction or elimination of antibiotics for this purpose, while showing reductions in percent infection, process variability and interference with yeast viability.

Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

A method for addressing process variability in a build-to-order, mass customization production environment. The method includes receiving an order for a product having a particular configuration defined by the order, initiating a production order specifically assigned to the order, fabricating the product based upon the production order, determining if an unrelated product order contains an identical product item configuration and automatically swapping identical product items contained on unrelated production orders to optimize overall production process objectives.

A system and method are provided for a PTAT cell with no resistors which can operate at low power, has less sensitivity to process variation, occupies less silicon area, and has low noise. Further, a system and method are provided to scale up the reference voltage and current through a cascade of unit cells. Still further, a system and method are provided for PTAT component to be fine-tuned, advantageously providing less process variability and less temperature sensitivity.

Systems and methods are disclosed for a stochastic model of mask process variability of a photolithography process, such as for semiconductor manufacturing. In one embodiment, a stochastic error model may be based on a probability distribution of mask process error. The stochastic error model may generate a plurality of mask layouts having stochastic errors, such as random and non-uniform variations of contacts. In other embodiments, the stochastic model may be applied to critical dimension uniformity (CDU) optimization or design rule (DR) sophistication.

A method for determining a blended color transform for use in producing printed colors on a color printer having at least four device color channels, comprising: forming first and second color transforms, wherein the first color transform produces printed colors that have a reduced sensitivity to color printer process variations in at least a first region of color space that includes a near-neutral color region, and wherein the second color transform produces printed colors that have a reduced image noise visibility in at least a second region of color space; defining a blending function which computes weighting values for the first and second color transforms as a function of input color values; and using a processor to determine the blended color transform by blending the first color transform and the second color transform, responsive to the blending function.

Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

A manufacturing method for the inductor / transformer is disclosed. A simulator is used to simulate the inductance, the quality factor, and the self-resonance frequency of said inductor / transformer to generate at least one group of the area size, the number of the conductive layer, the line width, the number of turns, and / or the line space of the conductive layers and the first conductive layer; the inductor / transformer is manufactured according to the factors. Thereafter, the Monte-Carlo simulation is used to initiate the process variability analysis of the factors of the conductive layer and the first conductive layer, and the geometric size of the inductor / transformer can be modulated according to the results of the process variability analysis during the manufacturing process, such that the inductor / transformer can be manufactured by the process of the generic logic circuit.

An improved automatic feedback control scheme enhances plasma spraying of powdered material through reduction of process variability and providing better ability to engineer coating structure. The present inventors discovered that controlling centroid position of the spatial distribution along with other output parameters, such as particle temperature, particle velocity, and molten mass flux rate, vastly increases control over the sprayed coating structure, including vertical and horizontal cracks, voids, and porosity. It also allows improved control over graded layers or compositionally varying layers of material, reduces variations, including variation in coating thickness, and allows increasing deposition rate. Various measurement and system control schemes are provided.

A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and / or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time.

An improved method and apparatus for blending process materials. Preferred embodiments of the present invention are directed to a process material contacting system to increase wetted surface area for liquid contact as well as increase forced convective mixing efficiency of the liquid mixture. Use of a novel process material contacting apparatus allows one solid feeding element to serve multiple process material tanks, thus reducing overall system costs and decreasing set-up time / process variability while increasing operational efficiency. According to a preferred embodiment of the present invention, rather than adding a process material to a volume of liquid held in a blending tank, the added process material is remotely blended with the liquid outside the process material tank.

Processing test results from a plurality of individual semiconductor testers by analyzing each test result at an adaptive test engine. A centralized system jointly analyzes all the test results from the plurality of individual semiconductor testers. The adaptive test engine or the centralized system identifies, based on the analysis of each test result or the joint analysis of all the test results, one or more of: a test environmental issue, a tester variability issue, a tester calibration issue, a product variability issue, and a manufacturing process variability issue. The adaptive test engine or the centralized system determines whether one or more of the plurality of individual semiconductor testers causes one or more of the identified issues or whether semiconductor products tested by the plurality of individual semiconductor testers causes one or more of the identified issues.

A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors.

Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.

Embodiments of the invention provide to apparatuses and media used in drug elution studies and methods for making and using them. One embodiment of the invention is a drug elution method that can be used for in-vitro studies of a matrix impregnated with a compound such as a drug blended polymer matrix. Such methods and materials can be used for example to assess and control the manufacturing process variability of drug eluting implantable devices such as cardiac leads.

Embodiments of the invention provide to apparatuses and media used in drug elution studies and methods for making and using them. Such methods and materials can be used for example to assess and control the manufacturing process variability of drug eluting implantable devices such as cardiac leads. One embodiment of the invention is a drug elution method that can be used for in-vitro studies of a matrix impregnated with a compound such as a drug blended polymer matrix. A related embodiment of the invention is an apparatus that is used for example to facilitate the practice of the above-noted methods by inhibiting the evaporation of dissolution media from the vessels in which elution is observed.

A method for optimizing the manufacturing of interconnects in microelectronic packages in the presence of sources of process variability. The method can estimate the contribution of multiple parameter to the quality of the interconnects, enabling the optimization of the manufacturing process.

Embodiments of the invention provide to apparatuses and media used in drug elution studies and methods for making and using them. Such methods and materials can be used for example to assess and control the manufacturing process variability of drug eluting implantable devices such as cardiac leads. One embodiment of the invention is a drug elution method that can be used for in-vitro studies of a matrix impregnated with a compound such as a drug blended polymer matrix. A related embodiment of the invention is an apparatus that is used for example to facilitate the practice of the above-noted methods by inhibiting the evaporation of dissolution media from the vessels in which elution is observed.