Rapid locking method for full digital phase-locked loop

Abstract

The invention relates to a rapid locking method for a full digital phase-locked loop, which is used for locking the frequency of the full digital phase-locked loop comprising a phase detection discriminator, a time-to-digit converter, a digital filter, a digital controlled oscillator and a frequency divider in a short time. The method is characterized by comprising the following steps: finding a control word controlling the frequency of the digital controlled oscillator by a designed algorithm; dividing the frequency of a clock output by the digital controlled oscillator which is controlled bythe control word to obtain a divided-frequency clock with the frequency approximate to a reference clock frequency; and then, controlling the digital controlled oscillator to lock based on a phase difference between the reference clock and the divided-frequency clock which are distinguished by the phase detection discriminator. The full digital phase-locked loop is provided with a rapid frequencycapture loop and a phase-locked loop which alternately work, i.e. firstly, the rapid frequency capture loop finishes frequency capture, and then, the phase-locked loop finishes accurate locking.

Description

technical field [0001] The invention relates to an all-digital phase-locked loop used in an embedded chip, in particular to a fast locking method of the all-digital phase-locked loop, which can greatly reduce the locking time of the phase-locked loop. Background technique [0002] With the development of integrated circuit deep submicron technology, people have higher and higher requirements on the performance and cost of embedded chips. The challenges of a series of issues such as high integration, portability, reliability and low cost have made the traditional analog phase-locked loop fully exposed its obvious disadvantages. Therefore, there is currently a trend to replace the voltage-controlled oscillator in the analog phase-locked loop with a digitally controlled oscillator (DCO), and replace the analog filter with a digital filter to form a new phase-locked loop called a full digital lock. phase ring. [0003] Such as figure 1 Shown is a commonly used all-digital pha...

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Problems solved by technology

However, the increase in the bandwidth of the PLL will deteriorate the jitter performance of the PLL output clock and the stability of the PLL system, and the locking time of the PLL is not ideal, at least dozens of reference clock cycles

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