Current starved DAC-controlled delay locked loop

Abstract

A delay locked loop circuit with improved restart features. The circuit includes a clock input (1120, a clock output (116), a divider circuit (114), phase detector (118) and control logic (124). The circuit includes a means (126) for implementing a binary search of outputs from the control logic (124) for generating a calibration bit, which is applied to the transmission on an output line (120).

Description

technical field [0001] The present invention relates to semiconductor circuits, and more particularly to an improved delay locked loop (DLL) design for power savings and fast shutdown and restart. Background technique [0002] The design of current controlled delay cells is relatively well known in the art. A pair of cascaded CMOS inverters, with an additional p-type and n-channel transistor inserted into the current path and reflected from the reference current, will establish a fixed delay through a cell. No matter how a conventional current-controlled DLL is designed, it has many disadvantages. The current value must be accurate and must match the delay circuit. Short delays for input signals require high operating currents. To compensate for other variations, such as voltage supply or temperature variations, high value current mirrors are required. These features increase power requirements. In addition, these systems suffer from noise interference. [0003] Under ...

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Problems solved by technology

Additionally, the control circuit must include a lock detector circuit

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