Circuit structure and method for realizing clock recovery on the basis of USB device

Abstract

The invention relates to a circuit structure and method for realizing clock recovery on the basis of a USB device. The circuit structure comprises a built-in oscillator module for generating oscillation signals; and a digital control logic module which includes a USB clock recovery unit for sampling the oscillation signals of the built-in oscillator and performing the clock recovery and a frequency adjustment unit for adjusting the oscillation frequency of the built-in oscillator according to a comparison result between USB signals and the oscillation signals of the built-in oscillator. By using the circuit structure and method for realizing the clock recovery on the basis of the USB device through such a structure, an accurate system clock can be generated, a frequency tracking feature is exhibited, a USB data transmission frequency is compared with the frequency of the built-in oscillator through adoption of the digital control logic module, the frequency of the built-in oscillator is automatically switched among a low-speed state, a medium-speed state and a high-speed state, the system precision and the stability are guaranteed, the production cost is decreased, and the application scope is wider.

Description

technical field [0001] The present invention relates to the field of clock recovery, in particular to the field of USB device clock recovery, in particular to a circuit structure and method for realizing clock recovery based on USB device. Background technique [0002] Most of the existing technologies are the following solutions: [0003] (1) Using an external crystal oscillator to provide an accurate clock for the circuit; [0004] (2) A phase-locked loop PLL design is adopted to generate a clock signal consistent with the frequency and phase of the serial data; [0005] (3) Adopt delay-locked loop DLL design to generate a clock signal consistent with serial data frequency and phase. [0006] Disadvantages of the above approach: [0007] (1) External crystal oscillator, the periphery is relatively complex, the error is large, and the cost is increased; [0008] (2) The PLL design of the phase-locked loop makes the circuit area relatively large, the overall design is mo...

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Problems solved by technology

[0007] (1) External crystal oscillator, the periphery is relatively complex, the error is large, and the cost is increased;

[0008] (2) The PLL design of the phase-locked loop makes the circuit area relatively large, the overall design is difficult, the locking time is long, it is sensitive to noise, and there are problems such as accumulation of phase difference errors;

[0009] (3) Delay-locked loop DLL design has poor jitter suppression performance, relatively limited locking range, high power consumption, and no frequency tracking characteristics

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