States encoding in multi-bit flash cells for optimizing error rate

a multi-bit flash cell and error rate optimization technology, applied in the field of flash memories, can solve the problems of reducing the number of orderings that can actually be used, 0” cannot be used, and ordering of bit patterns that require the threshold voltage to decreas

Inactive Publication Date: 2005-09-29
SANDISK IL
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  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0035] According to the present invention there is provided a method of of storing N bits of data, including the steps of: (a) providing ┌N/M┐ cells, wherein M is at least 3; and (b) programming each cell with up to M of the bits according to a valid, nonserial, error-rate-optimal bit ordering.
[0036] According to t

Problems solved by technology

However, there are restrictions put on the ordering because of the way the flash cells are programmed, and these restrictions reduce the number of orderings that can actually be used.
Second, assuming a design in which each bit resides in a different page, there are restrictions caused by the bits of a

Method used

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  • States encoding in multi-bit flash cells for optimizing error rate
  • States encoding in multi-bit flash cells for optimizing error rate
  • States encoding in multi-bit flash cells for optimizing error rate

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Embodiment Construction

[0066] The present invention is of a method of programming multi-bit flash cells.

[0067] The principles and operation of a multi-bit-cell flash memory device according to the present invention may be better understood with reference to the drawings and the accompanying description.

[0068] We now consider the question of what is a good ordering of the bit patterns in an n-bit MBC cell. There is no one clear-cut criterion to use for deciding what is “best”. Instead we present several different criteria to choose from. The best criterion to use in an actual design depends upon the requirements of the overall storage system, as is made clear in the discussion below.

[0069] We base our evaluation of orderings on the number of comparison operations required for reading the bits contained in an MBC cell. As already explained above, an SBC cell requires just one comparison of its threshold voltage value against a reference in order to determine the cell's data contents. A 2-bit MBC cell may...

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Abstract

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Description

[0001] This patent application claims the benefit of U.S. Provisional Patent Application No. 60 / 553,798, filed Mar. 14, 2004. This patent application also claims the benefit of U.S. Provisional Patent Application No. 60 / 611,873, filed Sep. 22, 2004. This patent application also is a continuation-in-part of US patent application Ser. No. 11 / 035,807 filed Jan. 18, 2005.FIELD AND BACKGROUND OF THE INVENTION [0002] The present invention relates to flash memories and, more particularly, to a method of storing data in multi-bit flash cells. [0003] Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements o...

Claims

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Application Information

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IPC IPC(8): G11C11/34G11C11/56
CPCG11C11/5621G11C2211/5648G11C29/00G11C11/5628G06F3/0679G11C16/0483G11C16/10
Inventor LASSER, MENAHEM
Owner SANDISK IL
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