Programmable logic device, and server

Abstract

A programmable logic device, and a server, which relate to the technical field of chip upgrading. A stage of second multi-path selection switch MUX2 is added before a first multi-path selection switch MUX0 between a complex programmable logic device (CPLD) and a platform controller hub (PCH) flash, in order to establish a hardware path between a baseboard management controller (BMC) and the PCH flash; moreover, a stage of third multi-path selection switch MUX3 is added before a fourth multi-path selection switch MUX1 between the CPLD and a BMC flash, in order to establish a hardware path between the PCH and a BMC chip, i.e., the BMC flash. Thus, a selection signal at the second multi-path selection switch MUX2 and the third multi-path selection switch MUX3 is realized, and the selection signal can be sent to the CPLD so as to complete the switching of a selection path. Therefore, during an upgrading process for BMC / PCH FW, the security of upgrading firmware is ensured, and hardware support is also provided for simplifying the upgrading process.

Description

Programmable logic device and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on October 16, 2023, with application number 202311338046.X, and application name “A Programmable Logic Device and Server”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of chip upgrade technology, and in particular to a programmable logic device and a server. Background Art

[0004] CPLD (Complex Programmable Logic Device), short for Complex PLD, is a more complex logic component than PLD. A CPLD is a digital integrated circuit that allows users to customize their logic functions based on their needs. Its basic design approach uses an integrated development software platform, schematics, hardware description languages, and other methods to generate the corresponding target file. This code is then transferred to the target chip via a download cable ("in-system" programming), realizing the designed digital system.

[0005] CPLD firmware (burned files) are stored internally on the chip, ensuring security. However, the firmware for the baseboard management controller (BMC) and integrated south bridge (PCH) is stored in external flash chips, making it vulnerable to attack or tampering. Therefore, improving the security and usability of BMC / PCH firmware burning has become a technical challenge for those skilled in the art.

[0006] Summary of the Invention

[0007] The embodiments of the present application provide a programmable logic device method, apparatus, electronic device, and computer-readable storage medium to solve the problem of how to improve the security and usability of burning the BMC / PCH FW.

[0008] The embodiment of the present application discloses a programmable logic device, which is configured with a first multiplexer switch, a second multiplexer switch, a third multiplexer switch, and a fourth multiplexer switch;

[0009] The programmable logic device is also equipped with a corresponding integrated south bridge and baseboard management controller;

[0010] The first multiplex switch is connected to the programmable logic device via a first selection signal line for the integrated south bridge;

[0011] The second multiplex switch is connected to the programmable logic device via a second selection signal line and a first main control signal line for the integrated south bridge respectively;

[0012] The third multiplex switch is connected to the programmable logic device via a second main control signal line and a third selection signal line for the baseboard management controller respectively;

[0013] The fourth multiplex switch is connected to the programmable logic device via a fourth selection signal line for the baseboard management controller;

[0014] The first multiplexer switch and the second multiplexer switch are connected via a first serial peripheral interface bus for the integrated south bridge;

[0015] The third multiplexer switch and the fourth multiplexer switch are connected via a second serial peripheral interface bus for the baseboard management controller;

[0016] The integrated south bridge is connected to the first multiplexer switch and the third multiplexer switch via a third main control signal line for the integrated south bridge and a fourth main control signal line for the baseboard management controller respectively;

[0017] The baseboard management controller is connected to the second multiplex switch and the fourth multiplex switch through a fifth main control signal line for the integrated south bridge and a sixth main control signal line for the baseboard management controller respectively.

[0018] In some embodiments, the integrated south bridge has a corresponding basic input and output system chip, and the first multiplexer is connected to the basic input and output system chip via a third serial peripheral interface bus for the integrated south bridge.

[0019] In some embodiments, the baseboard management controller is provided with a corresponding baseboard management controller chip, and the fourth multiplexer is connected to the baseboard management controller chip via a fourth serial peripheral interface bus for the baseboard management controller.

[0020] In some embodiments, a programmable logic device is provided with a platform firmware resilience system, and the programmable logic device is configured to:

[0021] When it is determined that the platform firmware elastic system is not responsible for signal control and receives an upgrade instruction sent by the baseboard management controller or its integrated south bridge, a selection signal is sent to the second multiplexer through the second selection signal line, and a selection signal is sent to the third multiplexer through the third selection signal line to establish a primary channel, and an upgrade operation is performed on the baseboard management controller chip based on the primary channel, or an upgrade operation is performed on the basic input and output system chip based on the primary channel.

[0022] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0023] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line to control the baseboard management controller to perform an upgrade operation on the baseboard management controller chip.

[0024] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0025] A low level signal is sent to the first multiplexer through the first selection signal line, and a high level signal is sent to the fourth multiplexer through the fourth selection signal line. The integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the baseboard management controller chip.

[0026] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0027] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0028] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0029] A high level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line. The baseboard management controller is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0030] In some embodiments, the programmable logic device is used to:

[0031] When it is determined that the platform firmware resilience system is responsible for signal control and the baseboard management controller fails, a selection signal is sent to the first multiplexer through the first selection signal line, a selection signal is sent to the second multiplexer through the second selection signal line, a selection signal is sent to the third multiplexer through the third selection signal line, and a selection signal is sent to the fourth multiplexer through the fourth selection signal line to build a secondary channel, and the baseboard management controller chip is upgraded based on the secondary channel.

[0032] In some embodiments, sending a selection signal to a first multiplexer through a first selection signal line, sending a selection signal to a second multiplexer through a second selection signal line, sending a selection signal to a third multiplexer through a third selection signal line, and sending a selection signal to a fourth multiplexer through a fourth selection signal line to construct a secondary channel, and upgrading a baseboard management controller chip based on the secondary channel includes:

[0033] Sending a low-level signal to the first multiplexer, and not sending a signal to the second, third, and fourth multiplexers, to control the integrated south bridge to send the upgraded firmware for the baseboard management controller chip to the basic input / output system chip;

[0034] A high level signal is sent to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer to control the platform firmware flexibility system to migrate the upgraded firmware from the basic input / output system chip to the baseboard management controller chip.

[0035] In some embodiments, the programmable logic device is further configured to:

[0036] A high level signal is sent to the first multiplexer and the second multiplexer, and no signal is sent to the second, third, and fourth multiplexers, to control the platform firmware elastic system to verify and upgrade the firmware.

[0037] In some embodiments, the programmable logic device is further configured to:

[0038] A low-level signal is sent to the first multiplexer and the fourth multiplexer, and no signal is sent to the second multiplexer and the third multiplexer, so as to operate the baseboard management controller and the integrated south bridge.

[0039] The embodiment of the present application further discloses a server, comprising a programmable logic device, wherein the programmable logic device is configured with a first multi-way selection switch, a second multi-way selection switch, a third multi-way selection switch, and a fourth multi-way selection switch;

[0040] The programmable logic device is also equipped with a corresponding integrated south bridge and baseboard management controller;

[0041] The first multiplex switch is connected to the programmable logic device via a first selection signal line for the integrated south bridge;

[0042] The second multiplex switch is connected to the programmable logic device via a second selection signal line and a first main control signal line for the integrated south bridge respectively;

[0043] The third multiplex switch is connected to the programmable logic device via a second main control signal line and a third selection signal line for the baseboard management controller respectively;

[0044] The fourth multiplex switch is connected to the programmable logic device via a fourth selection signal line for the baseboard management controller;

[0045] The first multiplexer switch and the second multiplexer switch are connected via a first serial peripheral interface bus for the integrated south bridge;

[0046] The third multiplexer switch and the fourth multiplexer switch are connected via a second serial peripheral interface bus for the baseboard management controller;

[0047] The integrated south bridge is connected to the first multiplexer switch and the third multiplexer switch via a third main control signal line for the integrated south bridge and a fourth main control signal line for the baseboard management controller respectively;

[0048] The baseboard management controller is connected to the second multiplex switch and the fourth multiplex switch through a fifth main control signal line for the integrated south bridge and a sixth main control signal line for the baseboard management controller respectively.

[0049] In some embodiments, the integrated south bridge has a corresponding basic input and output system chip, and the first multiplexer is connected to the basic input and output system chip via a third serial peripheral interface bus for the integrated south bridge.

[0050] In some embodiments, the baseboard management controller is provided with a corresponding baseboard management controller chip, and the fourth multiplexer is connected to the baseboard management controller chip via a fourth serial peripheral interface bus for the baseboard management controller.

[0051] In some embodiments, a programmable logic device is provided with a platform firmware resilience system, and the programmable logic device is configured to:

[0052] When it is determined that the platform firmware elastic system is not responsible for signal control and an upgrade instruction is received from the baseboard management controller or its integrated south bridge, a selection signal is sent to the second multiplexer through the second selection signal line, and a selection signal is sent to the third multiplexer through the third selection signal line to establish a primary channel. An upgrade operation is performed on the baseboard management controller chip based on the primary channel, or an upgrade operation is performed on the basic input and output system chip based on the primary channel.

[0053] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0054] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line to control the baseboard management controller to perform an upgrade operation on the baseboard management controller chip.

[0055] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0056] A low level signal is sent to the first multiplexer through the first selection signal line, and a high level signal is sent to the fourth multiplexer through the fourth selection signal line. The integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the baseboard management controller chip.

[0057] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0058] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0059] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0060] A high level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line. The baseboard management controller is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0061] In some embodiments, the programmable logic device is used to:

[0062] When it is determined that the platform firmware resilience system is responsible for signal control and the baseboard management controller fails, a selection signal is sent to the first multiplexer through the first selection signal line, a selection signal is sent to the second multiplexer through the second selection signal line, a selection signal is sent to the third multiplexer through the third selection signal line, and a selection signal is sent to the fourth multiplexer through the fourth selection signal line to build a secondary channel, and the baseboard management controller chip is upgraded based on the secondary channel.

[0063] In some embodiments, sending a selection signal to a first multiplexer through a first selection signal line, sending a selection signal to a second multiplexer through a second selection signal line, sending a selection signal to a third multiplexer through a third selection signal line, and sending a selection signal to a fourth multiplexer through a fourth selection signal line to construct a secondary channel, and upgrading a baseboard management controller chip based on the secondary channel includes:

[0064] Sending a low-level signal to the first multiplexer, and not sending a signal to the second, third, and fourth multiplexers, to control the integrated south bridge to send the upgraded firmware for the baseboard management controller chip to the basic input / output system chip;

[0065] A high level signal is sent to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer to control the platform firmware flexibility system to migrate the upgraded firmware from the basic input / output system chip to the baseboard management controller chip.

[0066] In some embodiments, the programmable logic device is further configured to:

[0067] A high level signal is sent to the first multiplexer and the second multiplexer, and no signal is sent to the second, third, and fourth multiplexers, to control the platform firmware elastic system to verify and upgrade the firmware.

[0068] In some embodiments, the programmable logic device is further configured to:

[0069] A low-level signal is sent to the first multiplexer and the fourth multiplexer, and no signal is sent to the second multiplexer and the third multiplexer, so as to operate the baseboard management controller and the integrated south bridge.

[0070] The embodiments of the present application include the following advantages:

[0071] In an embodiment of the present application, a second multiplexer switch MUX2 is added before the first multiplexer switch MUX0 between the programmable logic device CPLD and the integrated south bridge PCH Flash to open a hardware path between the baseboard management controller BMC and the integrated south bridge PCH Flash. At the same time, a third multiplexer switch MUX3 is added before the fourth multiplexer switch MUX1 between the programmable logic device CPLD and the BMC Flash to open a hardware path between the integrated south bridge PCH and the baseboard management controller chip BMC Flash. The select signals Select of MUX2 and MUX3 can be sent to the programmable logic device CPLD to complete the switching of the SPI path. With the above structure, during the upgrade process of the BMC / PCH FW, the security of the upgraded firmware is guaranteed and hardware support is provided for simplifying the upgrade process. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] FIG1 is a circuit topology diagram of a programmable logic device provided in an embodiment of the present application;

[0073] FIG2 is a schematic diagram of an upgrade process for a baseboard management controller / integrated south bridge provided in an embodiment of the present application. DETAILED DESCRIPTION

[0074] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0075] In order to enable those skilled in the art to better understand the embodiments of the present application, some technical terms involved in the embodiments of the present application are explained below.

[0076] A BMC (Baseboard Management Controller) is a specialized service processor that uses sensors to monitor the status of a computer, network server, or other hardware device and communicates with the system administrator through independent connections. The BMC is part of the Intelligent Platform Management Interface (IPMI) and is typically contained within the motherboard or main circuit board of the device being monitored.

[0077] The BMC's sensors measure internal physical variables such as temperature, humidity, power supply voltage, fan speed, communication parameters, and operating system (OS) function. If any of these variables exceed established limits, the administrator is notified. The administrator can then use remote control to take corrective action. The monitored device can be power-cycled or restarted when necessary. This allows a single administrator to remotely control numerous servers and other devices simultaneously, saving overall network costs and ensuring reliability.

[0078] A CPLD (Complex Programmable Logic Device) is a digital integrated circuit that allows users to customize their logic functions based on their needs. Its basic design approach uses an integrated development software platform, schematics, hardware description languages, and other methods to generate the corresponding target file. This code is then transferred to the target chip via a download cable ("in-system" programming), realizing the designed digital system and programmable logic device.

[0079] PCH (Platform Controller Hub, integrated southbridge) is the most important component of the motherboard chipset, aside from the northbridge. It's typically located below the CPU socket on the motherboard, near the PCI bus slots. This layout is based on the fact that it connects to many I / O buses, and being further away from the processor facilitates wiring and makes it easier to maintain the principle of equal length routing for signal lines.

[0080] RAID (Redundant Arrays of Independent Disks) means "an array of several independent disks with redundancy."

[0081] A disk array is a large-capacity disk group composed of many independent disks. The combined effect of individual disks providing data improves overall disk system performance. This technology divides data into segments and stores them separately on each hard drive.

[0082] Disk arrays also utilize the concept of parity checking, which allows data to be read even if any hard drive in the array fails. During data reconstruction, the data can be recalculated and re-placed onto a new hard drive.

[0083] The I2C bus is a simple, bidirectional, two-wire synchronous serial bus that uses only two wires to transmit information between devices connected to the bus.

[0084] The master device initiates data transfer on the bus and generates a clock to open the device for transmission. At this point, any addressed device is considered a slave. The relationship between master and slave, sender and receiver, on the bus is not constant, but depends on the direction of data transmission. If the host wants to send data to a slave device, it first addresses the slave device, then actively sends data to the slave, and finally terminates the data transfer. If the host wants to receive data from a slave device, it first addresses the slave device, then receives the data sent by the slave, and finally terminates the reception process. In this case, the host is responsible for generating the timing clock and terminating the data transfer.

[0085] Mailbox: The I2C channel used by the BMC / PCH to communicate with the CPLD, mainly transmitting various interactive information and instructions.

[0086] With the development of the Internet of Things, big data, and AI technologies, servers are playing an increasingly important role. As the server industry matures, nearly all server manufacturers can meet customer requirements for server functionality. Consequently, improving server security and usability has become a hot research topic for server manufacturers, hoping to provide a better customer experience and increase product competitiveness.

[0087] In order to meet security requirements, based on the NIST SP 800-193 standard, those skilled in the art have proposed the PFR (platform firmware resilience) function.

[0088] PFR uses CPLD as the core of the entire PFR technology. CPLD performs secure boot verification, upgrades, and recovery on the PCH / BMC flash image, enabling secure management of the entire platform. The PFR CPLD functions are summarized as follows:

[0089] Detection: Before starting, verify the BMC / PCH FW to ensure the correctness of the FW;

[0090] Upgrade: CPLD completes the verification of BMC / PCH upgrade files and the upgrade action;

[0091] Recovery: If the CPLD detects that the BMC / PCH FW is damaged, it will restore the damaged FW using the recovery image.

[0092] The programmable logic device CPLD and the integrated south bridge PCH can access the integrated south bridge chip PCH Flash in a time-sharing manner through the multiplexer MUXA. The programmable logic device CPLD and the baseboard management controller BMC can access the baseboard management controller chip BMC Flash in a time-sharing manner through the multiplexer MUXB. However, the baseboard management controller BMC and the integrated south bridge PCH do not have a direct interactive link to each other's chip Flash, and can only use the programmable logic device CPLD to achieve data movement between the peripheral interface buses. Therefore, in the topology of the relevant technology, under the premise of PFR enabling, the baseboard management controller BMC can upgrade the integrated south bridge PCH, the baseboard management controller BMC can upgrade the baseboard management controller BMC, and the integrated south bridge PCH can upgrade the integrated south bridge PCH.

[0093] Taking BMC upgrading PCH as an example, the upgrade process is as follows:

[0094] 1. The CPLD transfers Flash control to the BMC. The BMC Web uploads the PCH upgrade package and stores it in the BMC Flash.

[0095] 2. CPLD takes over BMC Flash control and verifies the PCH upgrade package;

[0096] 3. The CPLD takes over control of the PCH Flash and moves the PCH upgrade package from the BMC Flash to the PCH Flash.

[0097] 4. CPLD transfers Flash control to BMC / PCH, and the system runs normally.

[0098] Although the topology of the programmable logic device mentioned above meets the security requirements, it has at least two problems in terms of usability:

[0099] 1. The PFR CPLD requires verification of the BMC / PCH firmware, which increases the server startup time. Therefore, in some scenarios, customers prioritize fast server startup over security and request that PFR be disabled. While the server can operate normally in this scenario, according to current PFR logic, BMC / PCH upgrades cannot be completed without PFR enabled.

[0100] The BMC / PCH FW consists of a static area and a dynamic area. The static area is normally immutable, while the dynamic area stores configuration information and can be modified. The CPLD only verifies the static area and not the dynamic area. However, abnormal data in the dynamic area can affect BMC / PCH operation. Customers have experienced BMC verification errors but operational anomalies, preventing them from logging into the BMC Web. A BMC upgrade is required to resolve the issue, but upgrading the BMC requires logging into the BMC Web first. Currently, there is no upgrade path available, rendering the machine unusable and resulting in a poor user experience.

[0101] This application aims to study a PFR CPLD that, while meeting the current server security requirements, can complete the BMC / PCH FW upgrade through special means (escape channel) for customers' special application scenarios or some abnormal situations, eliminating the defects in the above solution, ensuring the normal use of the server, thereby improving the server's usability and improving the customer experience.

[0102] 1 , a circuit topology diagram of a programmable logic device provided in an embodiment of the present application is shown. The programmable logic device in the embodiment of the present application may be configured with a first multiplexer, a second multiplexer, a third multiplexer, and a fourth multiplexer; the programmable logic device is further configured with a corresponding integrated south bridge and a baseboard management controller; the first multiplexer is connected to the programmable logic device via a first selection signal line for the integrated south bridge; the second multiplexer is connected to the programmable logic device via a second selection signal line and a first main control signal line for the integrated south bridge, respectively; the third multiplexer is connected to the programmable logic device via a second main signal line and a third selection signal line for the baseboard management controller, respectively; the fourth The multiplexer is connected to the programmable logic device via a fourth selection signal line for the baseboard management controller; the first multiplexer is connected to the second multiplexer via a first serial peripheral interface bus for the integrated south bridge; the third multiplexer is connected to the fourth multiplexer via a second serial peripheral interface bus for the baseboard management controller; the integrated south bridge is connected to the first multiplexer and the third multiplexer respectively via a third main control signal line for the integrated south bridge and a fourth main control signal line for the baseboard management controller; the baseboard management controller is connected to the second multiplexer and the fourth multiplexer respectively via a fifth main control signal line for the integrated south bridge and a sixth main control signal line for the baseboard management controller.

[0103] In some embodiments, the integrated south bridge has a corresponding basic input and output system chip, and the first multiplexer is connected to the basic input and output system chip via a third serial peripheral interface bus for the integrated south bridge. That is, the first multiplexer can send a serial peripheral interface signal PCH SPI Signal to the basic input and output system chip via the third serial peripheral interface bus.

[0104] In some embodiments, the baseboard management controller is provided with a corresponding baseboard management controller chip, and the fourth multiplexer is connected to the baseboard management controller chip through a fourth serial peripheral interface bus for the baseboard management controller, that is, the fourth multiplexer can send a serial peripheral interface signal BMC SPI Signal to the baseboard management controller chip through the fourth serial peripheral interface bus.

[0105] Among them, the programmable logic device can send a selection signal PCH Flash Sel0 for the integrated south bridge chip PCH Flash to the first multiplexer through the first selection signal line, and can send a selection signal PCH Flash Sel1 for the integrated south bridge chip PCH Flash to the second multiplexer through the second selection signal line; can send a selection signal BMC Flash Sel1 for the baseboard management controller chip BMC Flash to the third multiplexer through the third selection signal line; can send a selection signal BMC Flash Sel0 for the baseboard management controller chip BMC Flash to the fourth multiplexer through the fourth selection signal line; can send a serial peripheral interface master control signal PCH SPI Master1 for the integrated south bridge to the second multiplexer through the first master control signal line, and can send a serial peripheral interface master control signal BMC SPI Master1 for the baseboard management controller to the third multiplexer through the second master control signal line; the integrated south bridge PCH can send a peripheral interface master control signal PCH SPI Master0 for the integrated south bridge to the first multiplexer through the third master control signal line; and can send a peripheral interface master control signal BMC SPI for the baseboard management controller to the third multiplexer through the fourth master signal line. Master2, the baseboard management controller can send the peripheral interface master control signal BMC SPI Master0 for the baseboard management controller to the fourth multiplexer through the sixth master control signal line; and send the peripheral interface master control signal PCH SPI Master2 for the integrated south bridge to the second multiplexer through the fifth master control signal line.

[0106] In an embodiment of the present application, a second multiplexer switch MUX2 is added before the first multiplexer switch MUX0 between the programmable logic device CPLD and the integrated south bridge PCH Flash to open a hardware path between the baseboard management controller BMC and the integrated south bridge PCH Flash. At the same time, a third multiplexer switch MUX3 is added before the fourth multiplexer switch MUX1 between the programmable logic device CPLD and the BMC Flash to open a hardware path between the integrated south bridge PCH and the baseboard management controller chip BMC Flash. The select signals Select of MUX2 and MUX3 can be sent to the programmable logic device CPLD to complete the switching of the SPI path. With the above structure, during the upgrade process of the BMC / PCH FW, the security of the upgraded firmware is guaranteed and hardware support is provided for simplifying the upgrade process.

[0107] Based on the above embodiment, a modified embodiment of the above embodiment is proposed. It should be noted that, in order to simplify the description, only the differences from the above embodiment are described in the modified embodiment.

[0108] In some embodiments of the present application, a programmable logic device is provided with a platform firmware elasticity system, and the programmable logic device is used to:

[0109] When it is determined that the platform firmware elastic system is not responsible for signal control and receives an upgrade instruction sent by the baseboard management controller or its integrated south bridge, a selection signal is sent to the second multiplexer through the second selection signal line, and a selection signal is sent to the third multiplexer through the third selection signal line to establish a primary channel, and an upgrade operation is performed on the baseboard management controller chip based on the primary channel, or an upgrade operation is performed on the basic input and output system chip based on the primary channel.

[0110] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0111] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line to control the baseboard management controller to perform an upgrade operation on the baseboard management controller chip.

[0112] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0113] A low level signal is sent to the first multiplexer through the first selection signal line, and a high level signal is sent to the fourth multiplexer through the fourth selection signal line. The integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the baseboard management controller chip.

[0114] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0115] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0116] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0117] A high level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line. The baseboard management controller is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0118] For example, on the hardware link, a new second multiplexer switch MUX2 is added and the PFR CPLD code is modified to implement a first-level channel: the first-level channel can be a channel that compromises security for ease of use, meeting the customer's need for BMC / PCH FW upgrade when PFR is not enabled.

[0119] Refer to Figure 2, which is a schematic diagram of an upgrade process for a baseboard management controller / integrated south bridge provided in an embodiment of the present application. When the programmable logic device CPLD determines that the PFR function is not enabled, the first-level channel is enabled, and the "PCH Flash Sel1" signal is used to select the SPI path between the BMC and MUX0 through MUX2, and the "BMC Flash Sel1" signal is used to select the SPI path between the PCH and MUX1 through MUX3.

[0120] When PCH Flash Sel0 is "0", that is, PCH Flash Sel0 is a low-level signal, and BMC Flash Sel0 is "0", that is, BMC Flash Sel0 is a low-level signal, the upgrade behavior in the first-level escape channel may include: 1. Normal operation of BMC and PCH, 2. BMC upgrades BMC, and PCH upgrades PCH.

[0121] When PCH Flash Sel0 is "1", that is, PCH Flash Sel0 is a high-level signal, and BMC Flash Sel0 is "0", that is, BMC Flash Sel0 is a low-level signal, the upgrade behavior in the first-level escape channel may include: BMC upgrades PCH.

[0122] When PCH Flash Sel0 is "0", that is, PCH Flash Sel0 is a low-level signal, and BMC Flash Sel0 is "1", that is, BMC Flash Sel0 is a high-level signal, the upgrade behavior in the first-level escape channel may include: PCH upgrades BMC.

[0123] In the embodiment of the present application, by constructing a first-level channel, the complexity of the upgrade process is reduced during the upgrade process for the BMC / PCH FW.

[0124] In some embodiments of the present application, a programmable logic device is used to:

[0125] When it is determined that the platform firmware resilience system is responsible for signal control and the baseboard management controller fails, a selection signal is sent to the first multiplexer through the first selection signal line, a selection signal is sent to the second multiplexer through the second selection signal line, a selection signal is sent to the third multiplexer through the third selection signal line, and a selection signal is sent to the fourth multiplexer through the fourth selection signal line to build a secondary channel, and the baseboard management controller chip is upgraded based on the secondary channel.

[0126] In some embodiments, sending a selection signal to a first multiplexer through a first selection signal line, sending a selection signal to a second multiplexer through a second selection signal line, sending a selection signal to a third multiplexer through a third selection signal line, and sending a selection signal to a fourth multiplexer through a fourth selection signal line to construct a secondary channel, and upgrading a baseboard management controller chip based on the secondary channel includes:

[0127] Sending a low-level signal to the first multiplexer, and not sending a signal to the second, third, and fourth multiplexers, to control the integrated south bridge to send the upgraded firmware for the baseboard management controller chip to the basic input / output system chip;

[0128] A high level signal is sent to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer to control the platform firmware flexibility system to migrate the upgraded firmware from the basic input / output system chip to the baseboard management controller chip.

[0129] In some embodiments, the programmable logic device is further configured to:

[0130] A high level signal is sent to the first multiplexer and the second multiplexer, and no signal is sent to the second, third, and fourth multiplexers, to control the platform firmware elastic system to verify and upgrade the firmware.

[0131] In some embodiments, the programmable logic device is further configured to:

[0132] A low-level signal is sent to the first multiplexer and the fourth multiplexer, and no signal is sent to the second multiplexer and the third multiplexer, so as to operate the baseboard management controller and the integrated south bridge.

[0133] For example, two MUX switches, a second multiplexer and a third multiplexer, are added to the hardware link, and the PFR CPLD code is modified to ultimately implement a two-stage channel:

[0134] Level 1 channel: Security compromises usability to meet customer needs for BMC / PCH firmware upgrades when PFR is disabled.

[0135] Secondary channel: When PFR is enabled and the BMC / PCH firmware fails, other channels are available to complete the BMC / PCH upgrade task.

[0136] Compared with the first-level escape channel, the second-level escape channel still has some PFR functions, ensuring the compatibility of safety and ease of use.

[0137] Referring to Figure 2, when the PFR CPLD determines that the PFR function is enabled, the refresh process needs to be enabled according to the normal PFR function. When there is a problem with the BMC / PCH and the normal refresh process cannot be used (the BMC verification is normal, but the operation is abnormal and the BMC Web cannot be logged in, in which case the BMC needs to be upgraded to solve the problem), a command is sent to the CPLD through the PCH to enable the secondary channel. The PFR CPLD controls the "PCH Flash Sel0", "PCH Flash Sel1", "BMC Flash Sel0", and "BMC Flash Sel1" signals to complete the refresh of the BMC FW. Specifically, when PCH Flash Sel0 is "0", that is, PCH Flash Sel0 is a low-level signal; PCH Flash Sel1, BMC Flash Sel0, and BMC Flash Sel1 are NA, that is, no signal is sent to the second multiplexer, the third multiplexer, and the fourth multiplexer. Then, the upgrade behavior of the secondary channel includes: the PCH uploads the BMC FW to the PCH Flash.

[0138] When PCH Flash Sel0 and PCH Flash Sel1 are "1", that is, PCH Flash Sel0 and PCH Flash Sel1 are high-level signals; BMC Flash Sel0 and BMC Flash Sel1 are NA, that is, no signal is sent to the third multiplexer and the fourth multiplexer, the upgrade behavior of the secondary channel includes: PFR CPLD verifies BMC FW.

[0139] When PCH Flash Sel0, PCH Flash Sel1, BMC Flash Sel0, and BMC Flash Sel1 are all 1, that is, PCH Flash Sel0, PCH Flash Sel1, BMC Flash Sel0, and BMC Flash Sel1 are high-level signals, the secondary channel upgrade behavior includes: the PFR CPLD moves the BMC firmware from the PCH flash to the BMC flash.

[0140] When PCH Flash Sel0 and BMC Flash Sel0 are "1", that is, PCH Flash Sel0 and BMC Flash Sel0 are high-level signals; PCH Flash Sel1 and BMC Flash Sel1 are NA, that is, no signal is sent to the second multiplexer switch and the third multiplexer switch, and the BMC and PCH operate normally.

[0141] In order to enable those skilled in the art to better understand the embodiments of the present application, an example is used below to illustrate the upgrade behavior based on the secondary channel.

[0142] First, the PFR CPLD pulls down PCH Flash Sel0. The PCH can connect to the BIOS Flash through MUX0, and then the PCH transfers the BMC FW to the Flash. Then, the PFR CPLD pulls up PCH Flash Sel0 and PCH Flash Sel1. The PFR CPLD can connect to the BIOS Flash through MUX2 and MUX0 to verify the BMC FW. Next, the PFR CPLD pulls up PCH Flash Sel0, PCH Flash Sel1, BMC Flash Sel0, and BMC Flash Sel1. At this time, the PFR CPLD connects to the BIOS Flash through MUX2 and MUX0, and to the BMC Flash through MUX3 and MUX1. The BMC FW can be moved from the BIOS Flash to the BMC Flash through the SPI Master. Finally, the PFR CPLD pulls down PCH Flash Sel0 and BMC Flash Sel0. The PCH can access the BIOS Flash through MUX0, and the BMC can access the BMC Flash through MUX1. The PCH and BMC can then operate normally.

[0143] It should be noted that the above examples are merely illustrative, and those skilled in the art may construct primary channels or secondary channels respectively through other pathways based on the first multi-way selection switch, the second multi-way selection switch, the third multi-way selection switch, and the fourth multi-way selection switch. The embodiments of the present application do not impose any limitation on this.

[0144] The embodiment of the present application further discloses a server, comprising a programmable logic device, wherein the programmable logic device is configured with a first multi-way selection switch, a second multi-way selection switch, a third multi-way selection switch, and a fourth multi-way selection switch;

[0145] The programmable logic device is also equipped with a corresponding integrated south bridge and baseboard management controller;

[0146] The first multiplex switch is connected to the programmable logic device via a first selection signal line for the integrated south bridge;

[0147] The second multiplex switch is connected to the programmable logic device via a second selection signal line and a first main control signal line for the integrated south bridge respectively;

[0148] The third multiplex switch is connected to the programmable logic device via a second main control signal line and a third selection signal line for the baseboard management controller respectively;

[0149] The fourth multiplex switch is connected to the programmable logic device via a fourth selection signal line for the baseboard management controller;

[0150] The first multiplexer switch and the second multiplexer switch are connected via a first serial peripheral interface bus for the integrated south bridge;

[0151] The third multiplexer switch and the fourth multiplexer switch are connected via a second serial peripheral interface bus for the baseboard management controller;

[0152] The integrated south bridge is connected to the first multiplexer switch and the third multiplexer switch via a third main control signal line for the integrated south bridge and a fourth main control signal line for the baseboard management controller respectively;

[0153] The baseboard management controller is connected to the second multiplex switch and the fourth multiplex switch through a fifth main control signal line for the integrated south bridge and a sixth main control signal line for the baseboard management controller respectively.

[0154] In some embodiments, the integrated south bridge has a corresponding basic input and output system chip, and the first multiplexer is connected to the basic input and output system chip via a third serial peripheral interface bus for the integrated south bridge.

[0155] In some embodiments, the baseboard management controller is provided with a corresponding baseboard management controller chip, and the fourth multiplexer is connected to the baseboard management controller chip via a fourth serial peripheral interface bus for the baseboard management controller.

[0156] In some embodiments, a programmable logic device is provided with a platform firmware resilience system, and the programmable logic device is configured to:

[0157] When it is determined that the platform firmware elastic system is not responsible for signal control and an upgrade instruction is received from the baseboard management controller or its integrated south bridge, a selection signal is sent to the second multiplexer through the second selection signal line, and a selection signal is sent to the third multiplexer through the third selection signal line to establish a primary channel. An upgrade operation is performed on the baseboard management controller chip based on the primary channel, or an upgrade operation is performed on the basic input and output system chip based on the primary channel.

[0158] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0159] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line to control the baseboard management controller to perform an upgrade operation on the baseboard management controller chip.

[0160] In some embodiments, performing an upgrade operation on a baseboard management controller chip based on a primary channel includes:

[0161] A low level signal is sent to the first multiplexer through the first selection signal line, and a high level signal is sent to the fourth multiplexer through the fourth selection signal line. The integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the baseboard management controller chip.

[0162] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0163] A low level signal is sent to the first multiplexer through the first selection signal line and a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0164] In some embodiments, performing an upgrade operation on a basic input / output system chip based on a primary channel includes:

[0165] A high level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line. The baseboard management controller is controlled based on the first level channel to perform an upgrade operation on the basic input and output system chip.

[0166] In some embodiments, the programmable logic device is used to:

[0167] When it is determined that the platform firmware resilience system is responsible for signal control and the baseboard management controller fails, a selection signal is sent to the first multiplexer through the first selection signal line, a selection signal is sent to the second multiplexer through the second selection signal line, a selection signal is sent to the third multiplexer through the third selection signal line, and a selection signal is sent to the fourth multiplexer through the fourth selection signal line to build a secondary channel, and the baseboard management controller chip is upgraded based on the secondary channel.

[0168] In some embodiments, sending a selection signal to a first multiplexer through a first selection signal line, sending a selection signal to a second multiplexer through a second selection signal line, sending a selection signal to a third multiplexer through a third selection signal line, and sending a selection signal to a fourth multiplexer through a fourth selection signal line to construct a secondary channel, and upgrading a baseboard management controller chip based on the secondary channel includes:

[0169] Sending a low-level signal to the first multiplexer, and not sending a signal to the second, third, and fourth multiplexers, to control the integrated south bridge to send the upgraded firmware for the baseboard management controller chip to the basic input / output system chip;

[0170] A high level signal is sent to the first multiplexer, the second multiplexer, the third multiplexer, and the fourth multiplexer to control the platform firmware flexibility system to migrate the upgraded firmware from the basic input / output system chip to the baseboard management controller chip.

[0171] In some embodiments, the programmable logic device is further configured to:

[0172] A high level signal is sent to the first multiplexer and the second multiplexer, and no signal is sent to the second, third, and fourth multiplexers, to control the platform firmware elastic system to verify and upgrade the firmware.

[0173] In some embodiments, the programmable logic device is further configured to:

[0174] A low-level signal is sent to the first multiplexer and the fourth multiplexer, and no signal is sent to the second multiplexer and the third multiplexer, so as to operate the baseboard management controller and the integrated south bridge.

[0175] As for the server embodiment, since it is basically similar to the editable logic device embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the editable logic device embodiment.

[0176] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0177] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the embodiments of this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0178] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0179] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A programmable logic device, characterized in that: A first multi-way selection switch, a second multi-way selection switch, a third multi-way selection switch and a fourth multi-way selection switch are configured; The programmable logic device is also configured with a corresponding integrated south bridge and baseboard management controller; The first multi-way selection switch is connected to the programmable logic device via a first selection signal line for the integrated south bridge; The second multi-way selection switch is connected to the programmable logic device through a second selection signal line and a first main control signal line for the integrated south bridge respectively; The third multi-way selection switch is connected to the programmable logic device through a second main control signal line and a third selection signal line for the baseboard management controller respectively; The fourth multi-way selection switch is connected to the programmable logic device via a fourth selection signal line for the baseboard management controller; The first multiplexer selection switch and the second multiplexer selection switch are connected via a first serial peripheral interface bus for the integrated south bridge; The third multiplexer switch and the fourth multiplexer switch are connected via a second serial peripheral interface bus for the baseboard management controller; The integrated south bridge is connected to the first multi-way selection switch and the third multi-way selection switch respectively through a third main control signal line for the integrated south bridge and a fourth main control signal line for the baseboard management controller; The baseboard management controller is connected to the second multi-way selection switch and the fourth multi-way selection switch through a fifth main control signal line for the integrated south bridge and a sixth main control signal line for the baseboard management controller, respectively.

2. The programmable logic device according to claim 1, characterized in that: The integrated south bridge has a corresponding basic input and output system chip, and the first multiplexer is connected to the basic input and output system chip via a third serial peripheral interface bus for the integrated south bridge.

3. The programmable logic device according to claim 2, characterized in that: The baseboard management controller is provided with a corresponding baseboard management controller chip, and the fourth multiplexer is connected to the baseboard management controller chip via a fourth serial peripheral interface bus for the baseboard management controller.

4. The programmable logic device according to claim 3, characterized in that: The programmable logic device is provided with a platform firmware elastic system, and the programmable logic device is used for: In response to determining that the platform firmware elastic system is not responsible for signal control and receiving an upgrade instruction sent by the baseboard management controller or the integrated south bridge to which it belongs, a selection signal is sent to the second multiplexer through a second selection signal line, and a selection signal is sent to the third multiplexer through a third selection signal line to construct a primary channel, and an upgrade operation is performed on the baseboard management controller chip based on the primary channel, or an upgrade operation is performed on the basic input and output system chip based on the primary channel.

5. The programmable logic device according to claim 4, characterized in that: The performing an upgrade operation on the baseboard management controller chip based on the primary channel includes: A low level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line to control the baseboard management controller to perform an upgrade operation on the baseboard management controller chip.

6. The programmable logic device according to claim 4, characterized in that: The performing an upgrade operation on the baseboard management controller chip based on the primary channel includes: A low level signal is sent to the first multiplexer through the first selection signal line, a high level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled based on the primary channel to perform an upgrade operation on the baseboard management controller chip.

7. The programmable logic device according to claim 4, characterized in that: Performing an upgrade operation on the basic input / output system chip based on the primary channel includes: A low level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled to perform an upgrade operation on the basic input and output system chip based on the primary channel.

8. The programmable logic device according to claim 4, characterized in that: Performing an upgrade operation on the basic input / output system chip based on the primary channel includes: A high level signal is sent to the first multiplexer through the first selection signal line, a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the baseboard management controller is controlled to perform an upgrade operation on the basic input and output system chip based on the primary channel.

9. The programmable logic device according to claim 4, characterized in that: The programmable logic device is used for: In response to determining that the platform firmware resilience system is responsible for signal control and the baseboard management controller fails, a selection signal is sent to the first multiplexer through a first selection signal line, a selection signal is sent to the second multiplexer through a second selection signal line, a selection signal is sent to the third multiplexer through a third selection signal line, and a selection signal is sent to the fourth multiplexer through a fourth selection signal line to build a secondary channel, and upgrade the baseboard management controller chip based on the secondary channel.

10. The programmable logic device according to claim 9, characterized in that: The method of sending a selection signal to the first multi-way selection switch through a first selection signal line, sending a selection signal to the second multi-way selection switch through a second selection signal line, sending a selection signal to the third multi-way selection switch through a third selection signal line, and sending a selection signal to the fourth multi-way selection switch through a fourth selection signal line to construct a secondary channel, and upgrading the baseboard management controller chip based on the secondary channel includes: Sending a low level signal to the first multiplexer, and not sending a signal to the second multiplex, the third multiplex, and the fourth multiplex, so as to control the integrated south bridge to send the upgrade firmware for the baseboard management controller chip to the basic input and output system chip; A high level signal is sent to the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer to control the platform firmware elastic system to migrate the upgrade firmware from the basic input / output system chip to the baseboard management controller chip.

11. The programmable logic device according to claim 10, characterized in that: The programmable logic device is also used to: send a high-level signal to the first multiplexer and the second multiplexer, and not send a signal to the second multiplexer, the third multiplexer and the fourth multiplexer, so as to control the platform firmware elasticity system to verify the upgraded firmware.

12. The programmable logic device according to claim 11, characterized in that: The programmable logic device is further used to: send a low level signal to the first multiplexer and the fourth multiplexer, and not send a signal to the second multiplexer and the third multiplex, so as to operate the baseboard management controller and the integrated south bridge.

13. A server, characterized in that: A programmable logic device is included, wherein the programmable logic device is configured with a first multi-way selection switch, a second multi-way selection switch, a third multi-way selection switch and a fourth multi-way selection switch; The programmable logic device is also configured with a corresponding integrated south bridge and baseboard management controller; The first multi-way selection switch is connected to the programmable logic device via a first selection signal line for the integrated south bridge; The second multi-way selection switch is connected to the programmable logic device through a second selection signal line and a first main control signal line for the integrated south bridge respectively; The third multi-way selection switch is connected to the programmable logic device through a second main control signal line and a third selection signal line for the baseboard management controller respectively; The fourth multi-way selection switch is connected to the programmable logic device via a fourth selection signal line for the baseboard management controller; The first multiplexer selection switch and the second multiplexer selection switch are connected via a first serial peripheral interface bus for the integrated south bridge; The third multiplexer switch and the fourth multiplexer switch are connected via a second serial peripheral interface bus for the baseboard management controller; The integrated south bridge is connected to the first multi-way selection switch and the third multi-way selection switch respectively through a third main control signal line for the integrated south bridge and a fourth main control signal line for the baseboard management controller; The baseboard management controller is connected to the second multi-way selection switch and the fourth multi-way selection switch through a fifth main control signal line for the integrated south bridge and a sixth main control signal line for the baseboard management controller, respectively.

14. The server according to claim 13, characterized in that: The integrated south bridge has a corresponding basic input and output system chip, and the first multiplexer is connected to the basic input and output system chip via a third serial peripheral interface bus for the integrated south bridge.

15. The server according to claim 14, characterized in that: The baseboard management controller is provided with a corresponding baseboard management controller chip, and the fourth multiplexer is connected to the baseboard management controller chip via a fourth serial peripheral interface bus for the baseboard management controller.

16. The server according to claim 15, characterized in that The programmable logic device is provided with a platform firmware elastic system, and the programmable logic device is used for: In response to determining that the platform firmware elastic system is not responsible for signal control and receiving an upgrade instruction sent by the baseboard management controller or the integrated south bridge, a selection signal is sent to the second multiplexer through a second selection signal line. A selection signal is sent to the third multi-way selection switch through a third selection signal line to construct a primary channel, and an upgrade operation is performed on the baseboard management controller chip based on the primary channel, or an upgrade operation is performed on the basic input and output system chip based on the primary channel.

17. The server according to claim 16, characterized in that The performing an upgrade operation on the baseboard management controller chip based on the primary channel includes: A low level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line to control the baseboard management controller to perform an upgrade operation on the baseboard management controller chip.

18. The server according to claim 16, characterized in that: The performing an upgrade operation on the baseboard management controller chip based on the primary channel includes: A low level signal is sent to the first multiplexer through the first selection signal line, a high level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled based on the primary channel to perform an upgrade operation on the baseboard management controller chip.

19. The server according to claim 16, characterized in that Performing an upgrade operation on the basic input / output system chip based on the primary channel includes: A low level signal is sent to the first multiplexer through the first selection signal line, and a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the integrated south bridge is controlled to perform an upgrade operation on the basic input and output system chip based on the primary channel.

20. The server according to claim 16, characterized in that Performing an upgrade operation on the basic input / output system chip based on the primary channel includes: A high level signal is sent to the first multiplexer through the first selection signal line, a low level signal is sent to the fourth multiplexer through the fourth selection signal line, and the baseboard management controller is controlled to perform an upgrade operation on the basic input and output system chip based on the primary channel.

21. The server according to claim 16, characterized in that The programmable logic device is used for: In response to determining that the platform firmware resilience system is responsible for signal control and the baseboard management controller fails, a selection signal is sent to the first multiplexer through a first selection signal line, a selection signal is sent to the second multiplexer through a second selection signal line, a selection signal is sent to the third multiplexer through a third selection signal line, and a selection signal is sent to the fourth multiplexer through a fourth selection signal line to build a secondary channel, and upgrade the baseboard management controller chip based on the secondary channel.

22. The server according to claim 21, characterized in that The method of sending a selection signal to the first multi-way selection switch through a first selection signal line, sending a selection signal to the second multi-way selection switch through a second selection signal line, sending a selection signal to the third multi-way selection switch through a third selection signal line, and sending a selection signal to the fourth multi-way selection switch through a fourth selection signal line to construct a secondary channel, and upgrading the baseboard management controller chip based on the secondary channel includes: Sending a low level signal to the first multiplexer, and not sending a signal to the second multiplex, the third multiplex, and the fourth multiplex, so as to control the integrated south bridge to send the upgrade firmware for the baseboard management controller chip to the basic input and output system chip; A high level signal is sent to the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer to control the platform firmware elastic system to migrate the upgrade firmware from the basic input / output system chip to the baseboard management controller chip.

23. The server according to claim 22, characterized in that The programmable logic device is also used for: A high level signal is sent to the first multiplexer and the second multiplexer, and no signal is sent to the second multiplexer, the third multiplexer, and the fourth multiplexer, so as to control the platform firmware elasticity system to verify the upgraded firmware.

24. The server according to claim 23, characterized in that The programmable logic device is also used for: A low level signal is sent to the first multiplexer and the fourth multiplexer, and no signal is sent to the second multiplexer and the third multiplexer, so as to operate the baseboard management controller and the integrated south bridge.

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