Interface test card, system and method

Abstract

The invention discloses an interface test card, system and method. The interface test card comprises a circuit board, a programmable logic device, a first interface and a second interface, wherein the programmable logic device, the first interface and the second interface are arranged on the circuit board; the first interface is used for connecting an upper computer; the second interface is used for connecting a PCIe protocol interface of the board card to be tested; a static logic module and a reconfigurable logic module run on the programmable logic device; the static logic module is connected with the reconfigurable logic module and the first interface; and the reconfigurable logic module is connected with the second interface. The static logic module and the reconfigurable logic module are operated through the programmable logic device, and test requirements of different board cards to be tested can be dynamically reconfigured through the interface test card to form a functional test card for PCIe protocol interface test. A complete server environment does not need to be built for each to-be-tested board card and a special hardware board card does not need to be obtained, so that the test period and the test cost of the PCIe protocol result can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of testing technologies, and particularly to an interface test card, a system, and a method. Background Art

[0002] The Peripheral Component Interconnect Express (PCIe) protocol interface of the internal board cards in a server usually uses a general unified interface in terms of physical form, such as a Multi-channel Input Output (Mini Cool Edge IO, MCIO) interface, etc., and the underlying protocol is the standard Peripheral Component Interconnect Express (PCIe) protocol. However, the function configurations of the PCIe protocol interfaces of different board cards are different. For example, both the motherboard and the backplane adopt PCIe protocol interfaces, but the board cards to be adapted are Non-Volatile Memory Host Controller Interface Specification (NVME) hard disks or PCIe network cards.

[0003] The PCIe protocol interfaces of the server motherboard and backplane need to be tested before being put into use. However, during the test, a test environment needs to be built for the board cards to be tested. For example, the upstream of the PCIe interface of the test board card needs to be connected to the processor, and the downstream needs to be connected to a PCIe device. Here, the PCIe device can be a PCIe hard disk, a network card, etc. For different types of PCIe protocol interfaces, a complete test environment needs to be developed and built, usually including building a complete server environment, developing or purchasing a dedicated PCIe hardware board card, and calling a test script under the operating system to implement the test of the PCIe protocol interface device. Using this method to test the PCIe protocol interface not only has a long development cycle for the PCIe hardware board card, but also has a high test cost. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to provide an interface test card, a system, and a method, aiming to solve the problems of long development cycle and high test cost in testing the PCIe protocol interface in the prior art.

[0005] In a first aspect, the embodiments of this application provide an interface test card, which includes: a circuit board, and a programmable logic device, a first interface, and a second interface disposed on the circuit board;

[0006] The first interface is used to connect to a host computer; the second interface is used to connect to the PCIe protocol interface of the board card to be tested;

[0007] A static logic module and a reconfigurable logic module are running on the programmable logic device;

[0008] When the programmable logic device runs the static logic module, it receives the reconfiguration bitstream file output by the host computer according to the test requirements of the board under test, and writes the reconfiguration bitstream file to the reconfigurable logic module;

[0009] When the programmable logic device runs the reconfigurable logic module, it forms the service logic function corresponding to the test requirements according to the reconfiguration bitstream file, constitutes a function test card corresponding to the test requirements, and uses the function test card to test the PCIe protocol interface of the board under test.

[0010] In the embodiments of the present application, by setting up an interface test card, the static logic module running on the programmable logic device in the interface test card receives the reconfiguration bitstream file output by the host computer according to the test requirements of the board under test, and writes the reconfiguration bitstream file to the reconfigurable logic module, so that the reconfigurable logic module understands the test requirements of the board under test. Then, according to the test requirements, it forms the service logic function corresponding to the test requirements through dynamic reconfiguration, constitutes a function test card corresponding to the test requirements, and uses the function test card to test the PCIe protocol interface of the board under test. There is no need to build a complete server environment and obtain dedicated hardware boards for each type of board under test, which can effectively reduce the test cycle and test cost of the PCIe protocol results.

[0011] In some implementation manners of the first aspect, a service logic layer and a software layer are provided in the reconfigurable logic module;

[0012] When the programmable logic device runs the service logic layer, it determines the service logic function based on the test requirements in the reconfiguration bitstream file; when the programmable logic device runs the software layer, it performs dynamic reconfiguration according to the service logic function to form a function test card corresponding to the test requirements.

[0013] The interface test card in the embodiments of the present application realizes the PCIe protocol interface test of the board under test by defining the service logic layer and the software layer in the reconfigurable logic module, using the service logic layer to generate the service logic function of the test process according to the test requirements, and then forming the service logic function corresponding to the test requirements through the dynamic reconfiguration of the software layer.

[0014] In some implementations of the first aspect, when the interface test card is a root endpoint device, the programmable logic device runs the software layer to execute sending the write test data packet to the service logic layer; the programmable logic device runs the software layer to execute reading the device information of the board under test and sending the device information to the service logic layer; the programmable logic device runs the service logic layer to execute determining a test result based on the write test data packet and the device information, and transmitting the test result to the host computer.

[0015] In the embodiment of the present application, when the interface test card is a root endpoint device, the software layer is used to read the device information of the board under test, and then the test result of the PCIe protocol interface of the board under test can be directly determined by combining the device information in the write test data packet, so as to implement the test of the PCIe protocol port when the interface test card is a root endpoint device.

[0016] In some implementations of the first aspect, when the interface test card is an endpoint device, the programmable logic device runs the software layer to execute sending network configuration information to the board under test, so that the board under test modifies the network configuration information of the interface test card; the programmable logic device runs the software layer to execute receiving the initialization instruction output by the board under test and executing the initialization process; the programmable logic device runs the software layer to execute receiving the write test data packet output by the board under test and sending the write test data packet to the service logic layer; the programmable logic device runs the service logic layer to execute feeding back a read test instruction to the software layer based on the write test data packet; the programmable logic device runs the software layer to execute packing the test instruction into a read test data packet and sending it to the board under test.

[0017] In the embodiment of the present application, the board under test modifies the network configuration information of the software layer of the interface test card to establish a communication connection between the interface test card and the board under test, and then the board under test sends a write test data packet to start the test, and the read and write functions of the software layer and the service logic layer are used to receive the write test data packet and send the read test data packet, so as to complete the test function of the PCIe protocol interface when the interface test card is an endpoint device and only has read and write functions.

[0018] In some implementations of the first aspect, the programmable logic device runs the service logic layer to execute storing the write test data packet.

[0019] In the embodiments of the present application, by virtualizing a virtual NVME storage layer and a virtual NVME software layer within the reconfigurable logic module, the MVNE interface of the board under test can be effectively tested, further expanding the test scenario. In addition, considering that during the NVNME interface test, an NVME hard disk needs to be separately set up for storing test data, while in the embodiments of the present application, the test data is stored through the virtual NVME storage layer, eliminating the need to set up an NVME hard disk and further reducing the cost of interface testing.

[0020] In some implementation manners of the first aspect, the interface test card further includes: a host computer communication unit, which is disposed on the circuit board and is respectively connected to the programmable logic device and the first interface;

[0021] A reconstruction management unit is disposed on the static logic module and is connected to the host computer communication unit and the reconfigurable logic module respectively through a communication bus;

[0022] The host computer communication unit is configured to receive the reconstruction bitstream file output by the host computer according to the board under test;

[0023] The programmable logic device runs the reconstruction management unit to execute writing the reconstruction bitstream file to the reconfigurable logic module.

[0024] In the embodiments of the present application, by defining the specific host computer communication unit within the static logic module, the connection between the host computer and the interface protocol card can be effectively established to realize the transmission of instructions, files, and data. And through the setting of the reconstruction management unit, the received reconstruction bitstream file can be effectively written, laying a foundation for the reconstruction of the service logic function within the reconfigurable logic module.

[0025] In some implementation manners of the first aspect, the static logic module further includes: a controller, which is connected to the host computer communication unit through the communication bus and is connected to the reconstruction management unit through the communication bus; the programmable logic device runs the controller to execute receiving the test instruction transmitted by the host computer communication unit and outputting a reconstruction instruction to the reconstruction management unit;

[0026] The interface test card further includes: a storage unit, which is disposed on the circuit board and is connected to the host computer communication unit through the communication bus and is connected to the reconstruction management unit through the communication bus; the programmable logic device runs the storage unit to execute storing the test instruction and the reconstruction bitstream file transmitted by the host computer communication unit;

[0027] The programmable logic device runs the reconstruction management unit to execute in response to the reconstruction instruction, extract the reconstruction bitstream file in the storage unit, and write the reconstruction bitstream file to the reconfigurable logic module.

[0028] In the embodiments of the present application, by setting a controller and a storage unit in the interface test card, various information input by the host computer can be stored, and the test process can be executed according to the logic of the interface test, which can prevent the test logic from being chaotic during the test and avoid affecting the test results.

[0029] In some implementation manners of the first aspect, the static logic module further includes: a PCIe control unit interface, which is respectively connected to the PCIe protocol interface of the board to be tested and the reconfigurable logic module; the programmable logic device runs the PCIe control unit interface to execute the transmission of the test file between the board to be tested and the reconfigurable logic module.

[0030] In a second aspect, the embodiments of the present application provide an interface test system, including a host computer and the interface test card described in any one of the above;

[0031] The interface test card is respectively connected to the PCIe protocol interface of the board to be tested and the host computer.

[0032] The technical effects obtained in the second aspect are similar to those obtained by the corresponding technical means in the first aspect, and will not be elaborated here.

[0033] In a third aspect, the embodiments of the present application provide an interface test method, which is applied to the interface test card, and the interface test method includes:

[0034] Receiving the reconstruction bitstream file output by the host computer according to the test requirements of the board to be tested;

[0035] Performing dynamic reconstruction according to the reconstruction bitstream file to form a test file corresponding to the test requirements, and using the test file to test the PCIe protocol interface of the board to be tested. Description of the Drawings

[0036] Figure 1 It is the first structural schematic diagram of the interface test card proposed by the embodiments of the present application;

[0037] Figure 2 It is the second structural schematic diagram of the interface test card proposed by the embodiments of the present application

[0038] Figure 3 It is the structural schematic diagram corresponding to the FPGA dynamic reconstruction technology;

[0039] Figure 4The third structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0040] Figure 5 The fourth structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0041] Figure 6 The fifth structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0042] Figure 7 The sixth structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0043] Figure 8 The seventh structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0044] Figure 9 The eighth structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0045] Figure 10 The ninth structural schematic diagram of the interface test card proposed by the embodiment of the present application;

[0046] Figure 11 The tenth structural schematic diagram of the interface test card proposed by the embodiment of the present application.

[0047] Explanation of reference numerals:

[0048] 10. Static logic module; 20. Reconfigurable logic module; 201. Business logic layer; 202. Software layer; 101. Host computer communication unit; 102. Reconfiguration management unit; 103. Controller; 104. Storage unit; 105. PCIe control unit interface. Detailed implementation manners

[0049] For the convenience of clearly describing the technical solutions of the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and roles. For example, the first chip and the second chip are only used to distinguish different chips, and do not limit their sequence. Those skilled in the art can understand that the terms "first" and "second" do not limit the quantity and execution order, and the terms "first" and "second" do not necessarily limit being different.

[0050] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0051] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single items or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c can be single or multiple.

[0052] Embodiments of an interface test card are proposed in the embodiments of the present application. Please refer to Figure 1 and Figure 2 , Figure 1 which is the first structural schematic diagram of the interface test card proposed in the embodiments of the present application, Figure 2 and which is the second structural schematic diagram of the interface test card proposed in the embodiments of the present application.

[0053] It should be understood that there are many types of devices using the PCIe protocol interface, and the functions of different devices using the PCIe protocol interface are not the same. Correspondingly, the test methods for the PCIe protocol interface are also different. For each device using the PCIe interface, a complete test server environment needs to be built for it, and the corresponding PCIe hardware board for the device needs to be developed or purchased, which will result in a long test cycle and high test cost for the device.

[0054] In the embodiments of the application, the interface test card includes: a circuit board 100, and a programmable logic device 200, a first interface, and a second interface provided on the circuit board;

[0055] The first interface is used to connect to a host computer; the second interface is used to connect to the PCIe protocol interface of the board to be tested;

[0056] A static logic module 10 and a reconfigurable logic module 20 are running on the programmable logic device 200.

[0057] The programmable logic device runs the static logic module 10 to receive the reconfiguration bitstream file output by the host computer according to the test requirements of the board under test, and writes the reconfiguration bitstream file to the reconfigurable logic module 20;

[0058] The programmable logic device runs the reconfigurable logic module 20 to perform dynamic reconfiguration according to the reconfiguration bitstream file to form the service logic function corresponding to the test requirements, constituting a function test card corresponding to the test requirements, and uses the function test card to test the PCIe protocol interface of the board under test.

[0059] It should be noted that the circuit board 100 is a carrier for the programmable logic device 200, the first interface, and the second interface. The circuit board 100 can adopt a conventional integrated circuit board. The programmable logic device 200 is a logic device with dynamic reconfiguration function. In this embodiment and the following embodiments, a Field Programmable Gate Array (FPGA) can be selected. Of course, other logic devices with dynamic reconfiguration function can also be selected, and specific limitations are not made here. The first interface is used to connect to the host computer and is an interface for realizing communication between the programmable logic device 200 and the host computer. The second interface is used to connect to the board under test and is an interface for realizing communication between the programmable logic device 200 and the board under test. The second interface is an interface for communicating using the PCIe protocol.

[0060] The static logic module 10 and the reconfigurable logic module 20 are functional modules running on the programmable logic device 200. The static logic module 10 is used to implement the basic functions of the test card. During the test process, the static logic module 10 can execute test-related processes, establish a connection with the host computer for information transmission, and coordinate and control test steps such as controlling the process of the reconfigurable logic module 20. Among them, the host computer can obtain the PCIe interface test requirements of the board under test, and specifically can obtain the test requirements through methods such as user input and directly extracting after establishing a connection with the board under test.

[0061] The reconfiguration bitstream file is a file used to reconstruct the service logic function in the interface test card. The internal of this reconfiguration bitstream file includes the test requirements of the PCIe protocol interface of the board under test. The test requirements can be data reading test, data writing test, communication function test, etc. of the PCIe protocol interface. The reconfiguration bitstream file can be set inside the reconfigurable logic module 20 by means of writing.

[0062] The service logic function is the function implemented by the programmable logic device 200, which is used to test the corresponding requirements of the PCIe protocol interface. This service logic function matches the test requirements of the board under test. Different service logic functions of the programmable logic device 200 result in different test processes and test results for the PCIe protocol interface.

[0063] For example, in the case of performing read / write tests on the PCIe protocol interface, the reconfigurable logic module 20 in the programmable logic device 200 can execute the service logic function to output files to the board under test or receive files input by the board under test, thereby performing read / write tests on the PCIe protocol interface of the board under test. Another example is that the reconfigurable logic module 20 in the programmable logic device 200 can receive the read test data packets fed back by the board under test and then output write test data packets to the board under test to complete the read / write tests on the PCIe protocol interface of the board under test.

[0064] It can be understood that the reconfigurable logic module 20 is used to implement different PCIe protocol interface test functions. The reconfigurable logic module 20 can be dynamically configured according to the test requirements of different boards under test to adjust the test requirements of the current interface test card to match those of the board under test, thereby testing the PCIe protocol interface of the board under test. The reconfigurable logic module 20 is provided with a dynamic reconfiguration technology, which is an FPGA configuration technology that allows the modification of the FPGA design in an operation by loading a partial configuration file, usually a partial bit file.

[0065] As Figure 3 shown, by downloading any one of the partial reconfigurable files A1.bit, A2.bit, A3.bit, and A4.bit to the reconfigurable module A, it is possible to change the function of the A logic block without offline of other functions of the FPGA. During this process, the static logic module 10 is not affected by the loading of the partial bit file. The content of the partial bit file will be written into the reconfigurable logic module 20. The bit file is equivalent to the reconfiguration bit stream file in the embodiments of the present application and includes the test function requirements of the PCIe protocol interface of the board under test.

[0066] In a specific implementation, the host computer can first determine the test requirements of the board to be tested and generate a corresponding reconfiguration bitstream file according to the test requirements. When establishing a connection with the interface test card, the reconfiguration bitstream file is sent to the programmable logic device 200; the programmable logic device runs the static logic module 10 to receive the reconfiguration bitstream file output by the host computer according to the test requirements of the board to be tested, and then writes the reconfiguration bitstream file to the reconfigurable logic module 20; the programmable logic device runs the reconfigurable logic module 20 to perform dynamic reconfiguration according to the test requirements in the reconfiguration bitstream file, form the service logic function corresponding to the test requirements when the reconfiguration is completed, constitute a function test card corresponding to the test requirements, and use the function test card to test the PCIe protocol interface of the board to be tested.

[0067] It should be noted that the board to be tested may be a main board or a backplane. When the board to be tested is a backplane and the PCIe protocol interface on the backplane needs to be tested, refer to Figure 1 , the interface test card can form a main board through the reconfigured function test card, and the backplane can be connected to the terminal device through an additional interface. The function test card (main board) can interact with the terminal device through the backplane provided with the PCIe protocol interface, so as to realize the test of the PCIe protocol interface on the backplane. In Figure 1 , the interface test card constitutes the main board, the board to be tested is the backplane, and the terminal device is a hard disk or a network card.

[0068] Of course, refer to Figure 2 , when the board to be tested is a main board and the PCIe protocol interface on the main board needs to be tested, at this time, the interface test card can form a terminal device through the reconfigured function test card, and the board to be tested interacts with the interface test card set on the terminal device through the PCIe protocol interface set by itself, so as to realize the test of the PCIe protocol interface on the main board. The terminal device can be set according to the actual test requirements, such as a hard disk or a network card, etc.

[0069] In the embodiment of the present application, according to the reconfiguration bitstream file output according to the test requirements, the reconfiguration bitstream file is written to the reconfigurable logic module, so that the reconfigurable logic module understands the test requirements of the board to be tested, and then generates the corresponding service logic function through dynamic reconfiguration according to the test requirements, constitutes a function test card corresponding to the test requirements, and uses the function test card to test the PCIe protocol interface of the board to be tested. The PCIe protocol interface of the board to be tested with different test requirements can be tested through the interface test card, without building a complete server environment for each board to be tested and obtaining dedicated hardware boards, which can effectively reduce the test cycle and test cost of the PCIe protocol result.

[0070] Furthermore, referring to Figure 4 , in the reconfigurable logic module 20 within the interface test card in the embodiments of the present application, a service logic layer 201 and a software layer 202 are provided;

[0071] The programmable logic device 200 runs the service logic layer 201 to determine service logic functions based on the test requirements within the reconfiguration bitstream file;

[0072] The programmable logic device 200 runs the software layer 202 to perform dynamic reconfiguration according to the service logic functions to form a function test card corresponding to the test requirements.

[0073] It should be noted that the service logic layer 201 and the software layer 202 are virtualized within the reconfigurable logic module 20. The service logic layer 201 can implement different service logic functions according to different test requirements, such as data operation processing, virtual device specific functions, etc., for testing the PCIe protocol interface. In addition, the service logic layer 201 can also transfer data between the software layer 202, the upper computer, and other modules.

[0074] In the embodiments of the present application, the software layer 202 mainly implements functions related to the PCIe protocol, configures the docking with the PCIe protocol interface of the board to be tested, and makes the test functions of the board to be tested match the test functions required by the PCIe protocol interface, so that the interface test card has the service logic functions corresponding to the test requirements. Of course, the software layer 202 can also extract the information input by the board to be tested, so that the information output by the board to be tested can be recognized by the service logic layer 201, thereby realizing the transmission of data, instructions and other information between the service logic layer 201 and the board to be tested. The software layer 202 can implement functions such as direct memory access (DMA) engine function, transaction layer packet (TLP) parsing, and status reading and control of the link training and status state machine (LTSSM).

[0075] And in the embodiments of the present application, the software layer 202 can also perform dynamic reconfiguration according to the test requirements of the board to be tested, that is, reconfigure the service logic functions of the interface test card according to the test requirements. The service logic functions correspond to the test requirements of the board to be tested, and the service logic functions are the test functions of the interface test card. Different test requirements of the board to be tested result in different service logic functions formed by the reconfiguration bitstream file within the service logic layer 201.

[0076] In the embodiments of the present application, by defining the service logic layer 201 and the software layer 202 within the reconfigurable logic module 20, the service logic layer 201 determines the service logic functions of the test process according to the test requirements, and then the software layer 202 performs overall dynamic reconfiguration on the programmable logic device according to the determined service logic functions to obtain a functional test card. By dynamically reconfiguring the programmable logic device in the interface test card through the service logic layer 201 and the software layer 202, the PCIe protocol interface test can be performed on the to-be-tested board cards with different test requirements through the interface test card, without building a complete server environment and obtaining dedicated hardware board cards for each to-be-tested board card, which can effectively reduce the test cycle and test cost of the PCIe protocol results.

[0077] It should be understood that the read / write test process of the PCIe protocol interface includes a data read test and a data write test. The read test data packet is a data packet used to test the data read function of the PICE protocol interface. This read test data packet is generated by the functional test card after dynamic reconfiguration according to the test function requirements parsed by the software layer 202 based on the service logic layer 201. The write test data packet is a data packet used to test the data write function of the PICE protocol interface. The write test data packet is generated by the to-be-tested board card and input into the reconfigurable logic module 20.

[0078] During the read / write test process, the programmable logic device 200 runs the service logic layer 201 to determine the service logic functions based on the test requirements within the reconfigured bitstream file; the programmable logic device 200 runs the software layer 202 to perform dynamic reconfiguration according to the service logic functions to form a functional test card; then the functional test card packs the test instructions corresponding to the read / write test in the service logic functions into a read test data packet and sends it to the to-be-tested board card to perform a read test on the PCIe protocol interface of the to-be-tested board card; when the to-be-tested device can normally receive the read test data packet, it can be determined that the read / write function of the PCIe communication interface of the to-be-tested board card is normal. The programmable logic device 200 runs the software layer 202 to receive the write test data packet input by the to-be-tested board card, and then sends the write test packet to the service logic layer 201. The programmable logic device 200 runs the service logic layer 201 to store the data. When the data storage of the service logic layer 201 is completed, it is determined that the write function of the PCIe protocol interface of the to-be-tested board card is normal.

[0079] In the embodiments of the present application, relevant data packets are output by the functional test card during the test process, thereby realizing the PCIe protocol interface test on the to-be-tested board card. And through the sending of the read test data packet and the receiving of the write test data packet, a complete test of the read / write function of the PCIe protocol interface can be realized.

[0080] In the embodiment of the interface test card in this application, the interface test card establishes a connection with the board card to be tested. Both the interface test card and the board card to be tested are devices using the PCIe protocol. These devices can be divided into a root complex (RC), an endpoint (EP), and a switch (SW) according to their functions and roles; the root complex is the starting point on the PCIe bus, responsible for initiating bus transactions and managing all devices on the bus. In a desktop computer or server system, the PCIe controller on the motherboard chipset or inside the processor usually plays the role of the root complex. In EP mode, the device plays the role of an endpoint or a subordinate, and the programmable logic device 200 runs to receive read and write operations for the local memory space. An endpoint is a terminal device on the PCIe bus, responsible for receiving requests from the root complex or other devices and performing data transmission accordingly. The terminal device in EP mode is usually an external device connected through a backplane, such as a graphics card, a network card, a storage controller, etc. Therefore, since the modes of the interface test card and the board card to be tested are different, the steps in the test process are also different. For example, in the mode where the interface test card is an RC, the interface test card can directly read the data information in the board card to be tested to determine the test result; while when the interface test card is a PE device, the interface test card can implement the read and write functions of data.

[0081] Regarding the different modes of the interface test card (the interface test card is a root endpoint device or an endpoint device), the test logic for the board card to be tested is also different. Therefore, in this embodiment, different test logics can also be set for different modes of the interface test card.

[0082] When the interface test card is a root endpoint device, the interface test card can obtain the device information of the board card to be tested at this time. Then, during the test process, the test result of the PCIe protocol interface of the board card to be tested can be directly determined. This device information can be the PCIe configuration information of the board card to be tested, the status information of the Link Training Status State Machine (LTSSM), the link rate information, the device type information of the board card to be tested, etc.

[0083] During the test process, the programmable logic device 200 running the software layer 202 can give the write test data packet input by the board card to be tested to the service logic layer 201; at the same time, the programmable logic device 200 running the software layer 202 can also directly read the device information of the board card to be tested and give it to the service logic layer 201. The programmable logic device 200 running the service logic layer 201 can extract the device information in the write test data packet, and then compare it with the device information directly read by the software layer 202, and then obtain the test result of the PCIe protocol interface.

[0084] Among them, the device information of the board under test exists in the written test data packet. When writing data through the PCIe protocol interface, due to the abnormality of the PCIe protocol interface, some data transmissions may be abnormal. At this time, by comparing the device information directly read with the device information transmitted by the PCIe protocol interface, it is possible to determine whether there is an abnormality in the PCIe protocol interface. For example, if the device information in the written test data packet is exactly the same as or within the allowable error range of the device information read by the software layer 202, it can be determined at this time that the PCIe protocol interface is normal.

[0085] In addition, since the interface test card is a root endpoint device, it can directly interact with the host computer for data. When the service logic layer 201 determines the test result of the PCIe protocol interface, the reconfigurable logic module 20 can upload the test result to the host computer.

[0086] In the specific test process, the programmable logic device 200 runs the software layer 202 to read the device information of the board under test, and then gives the device information to the service logic layer 201; at the same time, the programmable logic device 200 runs the service logic layer 201 to output corresponding read / write test instructions according to the service logic function. After being dynamically reconfigured by the software layer 202, the read / write test instructions are packaged into a read test data packet, and then the read test data packet is input to the board under test through the PCIe protocol interface. The board under test can also feedback a written test data packet when receiving the read / write test data packet. When the software layer 202 receives the written test data packet, it sends the written test data packet to the service logic layer 201. The service logic layer 201 can determine the test result of the PCIe protocol interface according to the device information read by the software layer 202 received and the device information in the read / write data packet, and then upload the test result to the host computer to complete the test.

[0087] In the embodiment of the present application, when the interface test card is a root endpoint device, the software layer 202 is used to read the device information of the board under test, and then the test result of the PCIe protocol interface of the board under test can be directly determined by combining the device information in the written test data packet, so as to realize the test of the PCIe protocol port when the interface test card is a root endpoint device.

[0088] In the embodiment of the present application, the interface test card can also complete the PCIe protocol interface test of the board under test in the PE mode, that is, when the interface test card is an endpoint device, so as to realize the test of the PCIe protocol interface when the interface test card only has read and write functions. When the interface test card is an endpoint device, it is necessary to first configure the communication protocol between the board under test and the interface test card, so as to realize the data transmission between the board under test and the interface test card. During this process, since the interface test card only has read and write functions, the board under test can adjust the network configuration information in the software layer 202 of the interface test card. After the adjustment is completed, the board under test can recognize the interface test card as a PCIe device, and normal data packet transmission can be carried out between the two.

[0089] In a specific implementation, when the interface test card is an endpoint device, the programmable logic device 200 running the software layer 202 can first send network configuration information to the board under test, and the board under test can feedback PCIe configuration instructions according to the received network configuration information. The programmable logic device 200 running the software layer 202 modifies the network configuration information of the interface test card according to the PCIe configuration instructions, so that data packets can be transmitted between the software layer 202 and the board under test. After the network configuration information of the interface test card is modified, the board under test can also output an initialization instruction. The programmable logic device 200 running the software layer 202 executes the initialization process after receiving the initialization instruction output by the board under test to prepare for the next interface test. In a specific test, the board under test can directly generate a write test data packet and then send the write test data packet to the software layer 202; when the programmable logic device 200 runs the software layer 202 and receives the write test data packet, it can send the write test data packet to the service logic layer 201 for storage, so as to complete the data write function test of the PCIe protocol interface of the board under test; the programmable logic device 200 running the service logic layer 201 can also feedback a read test instruction to the software layer 202 based on the write test data packet; the programmable logic device 200 running the software layer 202 can package the test instruction into a read test data packet and send it to the board under test, so as to complete the data read function test of the board under test. In addition, during the test process when the interface test card is an endpoint device, the board under test may be a root endpoint device; if the board under test is a root endpoint device at this time, when the board under test receives the read test data packet, it can recognize that both the data read function and the data write function of the PCIe protocol interface are normal, and then feedback the test result to the host computer.

[0090] In the embodiment of the present application, the network configuration information of the interface test card software layer 202 is modified by the to-be-tested board, a communication connection is established between the interface test card and the to-be-tested board, and then the to-be-tested board sends a write test data packet to start the test. The read and write functions of the software layer 202 and the service logic layer 201 are used to receive the write test data packet and send the read test data packet, so as to complete the test function of the PCIe protocol interface when the interface test card only has read and write functions as an endpoint device.

[0091] In summary, the interface test card in the embodiment of the present application can implement the test function of the PCIe protocol interface in different RC or PE modes, further improving the applicability of the interface test card test.

[0092] It should be understood that the PCIe protocol interface is an interface for data transmission using the PCIe protocol, and the PCIe protocol interface can be a common PCIe interface, an NVME interface, etc. For different interfaces, the service logic layer 201 and the software layer 202 in the reconfigurable logic module 20 can be virtualized into layer structures with different functions.

[0093] In the embodiment of the present application, with reference to Figure 5 , when the to-be-tested board uses an NVME interface, a virtual NVME storage layer and a virtual NVME software layer can be set in the reconfigurable logic module 20 to correspond to the service logic layer 201 and the software layer 202 respectively.

[0094] When the board under test uses the NVME interface, the host computer first writes the reconfigurable logic into the reconfigurable logic module 20 in the interface test card by outputting a bitstream file, thereby establishing the NVME storage layer and the virtual NVME software layer. After the device under test is connected to the interface test card, the virtual NVME software layer modifies the network configuration information so that the board under test recognizes the interface test card as an NVME hard disk, and then the board under test performs NVME initialization on the interface test card. The virtual NVME software layer receives the commands related to initialization and executes the initial process, and gives feedback during the execution of the initial process to complete the initialization process. After the execution of the initialization process is completed, the board under test can directly generate an NVME write test data packet and then send the NVME write test data packet to the virtual NVME software layer; the programmable logic device 200 running the virtual NVME software layer can extract the test data when receiving the write test data packet, and then send the test data to the virtual NVME storage module layer for storage, thereby completing the data write function test of the NVME interface of the board under test. Then the board under test can issue a read data request. The programmable logic device 200 running the virtual NVME software layer parses the request when receiving the read data request, extracts the test data corresponding to the request from the virtual NVME storage module layer, and packs the test data into an NVME read test data packet and sends it to the board under test to complete the test of the NVME interface.

[0095] In the embodiment of the present application, the programmable logic device 200 running the virtual NVME storage layer and the virtual NVME software layer virtualized in the reconfigurable logic module 20 can effectively test the NVME interface of the board under test and further expand the test scenario. In addition, considering that during the NVME interface test process, an NVME hard disk needs to be separately set for storing test data, while in the embodiment of the present application, the test data is stored through the virtual NVME storage layer without setting an NVME hard disk, further reducing the cost of interface testing.

[0096] Refer to Figure 6 , when the board under test uses the PCIe interface, the programmable logic device 200 running the reconfigurable logic module 20 can set a virtual network card core layer and a virtual PCIe network card software layer in the reconfigurable logic module 20 corresponding to the service logic layer 201 and the software layer 202 respectively.

[0097] When the board under test uses a PCIe interface, the host computer can use the reconfigured bitstream file to first flash the reconfigurable logic into the interface test card to implement the virtual network card core layer and the virtual PCIe network card software layer. After the board under test is connected to the interface test card, the programmable logic device 200 runs the virtual PCIe network card software layer to modify the network configuration information, so that the board under test recognizes the interface test card as a PCIe network card. Subsequently, the board under test sends a configuration read instruction to the interface test card. When the programmable logic device 200 runs the virtual PCIe network card software layer and receives the read instruction, it returns the configuration information. After the board under test reads the configuration information, it sends a network data packet to the interface test card as a write test data packet according to the configuration information of the interface test card. The virtual PCIe network card software layer parses the received network data packet, extracts the test data and sends it to the virtual network card core layer. The programmable logic device 200 runs the virtual network card core layer to parse and calculate the return result data according to the packet content and feedback it to the virtual PCIe network card software layer. The programmable logic device 200 runs the virtual PCIe network card software layer to package the result data into a read data test packet and send it to the board under test, thus completing the PCIe interface test.

[0098] In the embodiment of the present application, by virtualizing the virtual network card core layer and the virtual PCIe network card software layer within the reconfigurable logic module 20, the PCIe interface of the board under test can be effectively tested, and the test scenario can be further expanded.

[0099] In the embodiment of the present application, the static logic module 10 not only needs to write the reconfigured bitstream file to the reconfigurable logic module 20, but also needs to communicate with the host computer, so as to transmit data or instructions with the host computer. For example, the transmission of information such as starting the test, stopping the test, reconfiguring the bitstream file, and feedbacking the test result.

[0100] Refer to Figure 7 , in the embodiment of the present application, the interface test card further includes: a host computer communication unit 101, which is arranged on the circuit board 100 and is respectively connected to the programmable logic device 200 and the first interface, and is used to receive the reconfigured bitstream file output by the host computer according to the board under test;

[0101] A reconfiguration management unit 102 is arranged on the static logic module 10. The reconfiguration management unit 102 is respectively connected to the host computer communication unit 101 and the reconfigurable logic module 20 through a communication bus. The programmable logic device 200 runs the reconfiguration management unit 102 to flash the reconfigured bitstream file to the reconfigurable logic module 20.

[0102] Among them, the host computer communication unit 101 is a unit inside the interface test card dedicated to data interaction with the host computer. The host computer communication unit 101 can establish a connection with the host computer through the first interface and the connection line, or can establish a connection with the host computer wirelessly. The host computer communication unit 101 can establish a connection with the reconstruction management unit 102 through the data bus provided in the interface test card. The communication bus provides a standard communication interface to achieve direct communication between each module and unit. The reconstruction management unit 102 is mainly a unit for managing the reconstruction of the service logic function inside the reconfigurable logic module 20. The reconstruction management unit 102 includes a configuration interface inside, and can write the reconstruction bitstream file to the reconfigurable logic module 20.

[0103] Before performing the PCIe protocol interface test, the host computer can generate a corresponding reconstruction bitstream file according to the functional requirements of the board to be tested, and then input the reconstruction bitstream file into the reconstruction management unit 102 through the host computer communication unit 101. When the programmable logic device 200 runs, the reconstruction management unit 102, upon receiving the reconstruction bitstream file, writes the reconstruction bitstream file to the reconfigurable logic module 20, thereby completing the reconstruction of the service logic function in the reconfigurable logic module 20 to form a function test card corresponding to the test requirements. And after the PCIE protocol interface test is completed, the programmable logic device 200 runs, and the reconfigurable logic module 20 can also transmit the test result to the host computer communication unit 101 through the communication bus, and then feedback the test result to the host computer through the host computer communication unit 101.

[0104] In the embodiment of the present application, by defining the host computer communication unit 101, the host computer can be effectively connected to the interface protocol card to realize the transmission of instructions, files and data. And through the setting of the reconstruction management unit 102, the reconstruction bitstream file received by the host computer communication unit 101 can be effectively written, laying a foundation for the reconstruction of the service logic function in the reconfigurable logic module 20.

[0105] In the embodiment of the present application, with reference to Figure 8 , the static logic module 10 further includes: a controller 103, connected to the host computer communication unit 101 through the communication bus and connected to the reconstruction management unit 102 through the communication bus, for receiving the test instruction transmitted by the host computer communication unit 101 and outputting a reconstruction instruction to the reconstruction management unit 102;

[0106] The interface test card further includes: a storage unit 104, which is disposed on the circuit board, communicates with the host computer communication unit 101 through the communication bus, and is connected to the reconstruction management unit 102 through the communication bus, and is used to store the test instructions transmitted by the host computer communication unit 101 and the reconstruction bitstream file;

[0107] The programmable logic device 200 runs the reconstruction management unit 102 to execute in response to the reconstruction instruction to extract the reconstruction bitstream file in the storage unit and write the reconstruction bitstream file to the reconfigurable logic module.

[0108] It should be understood that during the PCIe protocol interface test, a large amount of data is input to the interface test card, specifically including test instructions output by the host computer, reconstruction bitstream files, etc. During the actual test process, it needs to be executed in a certain process sequence. The controller 103 is mainly used to parse the host computer instructions and forward them through the communication bus, and trigger each unit to execute relevant instructions to maintain the overall process of the interface test. The storage unit 104 is a structure for storing the data received by the interface test card. The storage unit 104 can store the instructions output by the host computer, the reconstruction bitstream file, and test-related data.

[0109] During the actual test process, the reconstruction bitstream file output by the host computer through the host computer communication unit 101 is first stored inside the storage unit 104. When the board under test is connected to the interface test card, the host computer can input a test instruction through the host computer communication unit 101. The test instruction is received by the programmable logic device 200. At this time, the programmable logic device 200 running the controller 103 can determine that the board under test has been connected to the interface test card, and output a reconstruction instruction to the reconstruction management unit 102. When the programmable logic device 200 runs the reconstruction management unit 102 and receives the reconstruction instruction, the programmable logic device 200 runs the reconstruction management unit 102 to extract the reconstruction bitstream file from the storage unit 104 through the communication bus, and then writes the reconstruction bitstream file to the reconfigurable logic module 20.

[0110] In the embodiment of the present application, by setting the controller 103 and the storage unit 104 in the interface test card, various information input by the host computer can be stored, and the test process can be executed according to the logic of the interface test, which can prevent the test logic from being chaotic during the test and avoid affecting the test results.

[0111] Refer to Figure 9, in the embodiment of the present application, the static logic module 10 further includes: a PCIe control unit interface 105, which is respectively connected to the PCIe protocol interface of the board under test and the reconfigurable logic module, and is used to transmit test files between the board under test and the reconfigurable logic module.

[0112] It can be understood that there may be a mismatch between the interfaces of the board under test and the reconfigurable logic module 20. For example, the configuration interface is not normally open or the TLP data interface is not normally open. When the configuration interface is not open, the board under test cannot configure the software layer 202 inside the reconfigurable logic module 20, which in turn leads to a protocol mismatch between the software layer 202 and the PCIe protocol interface, and data transmission cannot be performed.

[0113] It should be noted that the PCIe control unit interface 105 is a structure for controlling data transmission between the interface test card and the board under test. The PCIe control unit interface 105 is internally provided with a structure from the transaction layer to the physical layer, which can implement the basic functions of the PCIe link. For example, the PCIe control unit interface 105 can open the TLP data interface and the configuration interface in the software layer 202 of the reconfigurable logic module 20, so that the software layer 202 matches the PCIe protocol interface, and then configure data interaction between the software layer 202 and the board under test to implement the configuration of the software layer 202; the PCIe control unit interface 105 can also perform data transmission between the software layer 202 and the board under test after the configuration of the software layer 202 is completed.

[0114] In the embodiment of the present application, the setting of the PCIe control unit interface 105 can open the TLP data interface and the configuration interface, so that the reconfigurable logic module 20 matches the board under test, so as to prevent the board under test from being unable to perform parameter configuration on the software layer 202 or unable to perform data transmission with the reconfigurable logic module 20.

[0115] In Figure 8In it, the reconfigured bitstream file output by the host computer through the host computer communication unit 101 is first stored inside the storage unit 104. When the board under test is connected to the interface test card, the host computer can input a test instruction through the host computer communication unit 101. This test instruction is received by the programmable logic device 200. At this time, the controller 103 running on the programmable logic device 200 can determine that the board under test has been connected to the interface test card and output a reconfiguration instruction to the reconfiguration management unit 102. When the reconfiguration management unit 102 receives the reconfiguration instruction, the reconfiguration management unit 102 running on the programmable logic device 200 can extract the reconfigured bitstream file from the storage unit 104 through the communication bus, and then flash the reconfigured bitstream file to the reconfigurable logic module 20. The service logic layer 201 in the reconfigurable logic module 20 running on the programmable logic device 200 can determine the service logic function based on the test requirements in the reconfigured bitstream file; the software layer 202 running on the programmable logic device 200 can form the service logic function corresponding to the test requirements according to the reconfigured bitstream file, constituting a function test card corresponding to the test requirements. The function test card can send test-related data packets to the board under test or receive data packets output by the board under test to test the PCIe protocol interface of the board under test. When the function test card outputs test-related data packets and the device under test can normally receive and read the test data packets, it can be determined that the read-write function of the PCIe communication interface of the board under test is normal. The software layer 202 running on the programmable logic device 200 receives the write test data packet input by the board under test, and then sends the write test packet to the service logic layer 201. The service logic layer 201 is stored by the programmable logic device 200 running the service logic layer 201. When the data storage of the service logic layer 201 is completed, it is determined that the write function of the PCIe protocol interface of the board under test is normal; thus, the test of the PCIe protocol interface is completed.

[0116] In addition, in the embodiments of the present application, there are also differences in the complete test card structures set for different PCIe protocol interfaces. Refer to Figure 10 and Figure 11 , Figure 10 is the ninth structural schematic diagram of the interface test card proposed in the embodiments of the present application; Figure 11 is the tenth structural schematic diagram of the interface test card proposed in the embodiments of the present application. There are significant differences in the service logic layer 201 and the software layer 202 provided inside the reconfigurable logic module 20, and thus different PCIe protocol interfaces are tested. In Figure 10 and Figure 11 , the specific functions of the static logic module 10 can refer to the discussion of the above static logic module 10; the specific functions of the reconfigurable logic module 20 can refer to the discussion of the above reconfigurable logic module 20, and will not be elaborated here.

[0117] On the other hand, an embodiment of the present application further provides an interface test system, including a host computer and the interface test card described in the claims; the interface test card is respectively connected to the PCIe protocol interface of the to-be-tested board card and the host computer. The interface test system can implement the functions in any embodiment of the above interface test card, which will not be elaborated here.

[0118] On the other hand, an embodiment of the present application further provides an interface test method, which is applied to the interface test card. The interface test card includes: a circuit board, a programmable logic device, a first interface, and a second interface provided on the circuit board; the first interface is used to connect to the host computer; the second interface is used to connect to the PCIe protocol interface of the to-be-tested board card; the interface test method includes:

[0119] S10: Receive the reconstructed bitstream file output by the host computer according to the test requirements of the to-be-tested board card;

[0120] S20: Form the service logic function corresponding to the test requirements according to the reconstructed bitstream file, constitute a function test card corresponding to the test requirements, and use the function test card to test the PCIe protocol interface of the to-be-tested board card.

[0121] The specific interface test method is as follows: The host computer can first determine the test requirements of the to-be-tested board card and generate a corresponding reconstructed bitstream file according to the test requirements. When establishing a connection with the interface test card, the reconstructed bitstream file is sent to the static logic module; the programmable logic device runs the static logic module to receive the reconstructed bitstream file output by the host computer according to the test requirements of the to-be-tested board card, and then writes the reconstructed bitstream file to the reconfigurable logic module; the programmable logic device runs the reconfigurable logic module to perform dynamic reconstruction according to the test requirements in the reconstructed bitstream file to form the service logic function corresponding to the test requirements, and can constitute a function test card corresponding to the test requirements when the reconstruction is completed, and use the function test card to test the PCIe protocol interface of the to-be-tested board card.

[0122] In the embodiments of the present application, by setting up an interface test card, the static logic module in the interface test card is used to receive the reconstructed bitstream file output by the host computer according to the test requirements of the board under test, and the reconstructed bitstream file is flashed into the reconfigurable logic module, so that the reconfigurable logic module understands the test requirements of the board under test, and then generates the corresponding service logic function through dynamic reconfiguration, thereby constituting a function test card corresponding to the test requirements. Using the function test card to test the PCIe protocol interface of the board under test, the PCIe protocol interface of the board under test with different test requirements can be tested through the interface test card, without building a complete server environment and obtaining dedicated hardware boards for each board under test, which can effectively reduce the test cycle and test cost of the PCIe protocol results.

[0123] For the interface test methods under different structures of the above interface test card, the specific application logic of the above interface test card can be referred to, and details are not described herein again.

[0124] The above specific implementation manners further elaborate the purpose, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above are only the specific implementation manners of the embodiments of the present application, and are not used to limit the protection scope of the embodiments of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. An interface test card, characterized in that, The interface test card includes: a circuit board, a programmable logic device, a first interface, and a second interface disposed on the circuit board; The first interface is used to connect to a host computer; the second interface is used to connect to the PCIe protocol interface of the board to be tested; A static logic module and a reconfigurable logic module are running on the programmable logic device; The programmable logic device runs the static logic module to receive the reconfiguration bitstream file output by the host computer according to the test requirements of the board to be tested, and writes the reconfiguration bitstream file to the reconfigurable logic module; the test requirements are read / write test requirements or communication test requirements; The programmable logic device runs the reconfigurable logic module to form the service logic function corresponding to the test requirements according to the reconfiguration bitstream file, constitutes a function test card corresponding to the test requirements, and uses the function test card to test the PCIe protocol interface of the board to be tested.

2. The interface test card according to claim 1, characterized in that, A service logic layer and a software layer are provided in the reconfigurable logic module; The programmable logic device runs the service logic layer to determine the service logic function based on the test requirements in the reconfiguration bitstream file; The programmable logic device runs the software layer to perform dynamic reconfiguration according to the service logic function to constitute a function test card corresponding to the test requirements.

3. The interface test card according to claim 2, characterized in that, When the interface test card is a root endpoint device, the programmable logic device runs the software layer to send a write test data packet to the service logic layer; The programmable logic device runs the software layer to read the device information of the board to be tested and send the device information to the service logic layer; The programmable logic device runs the service logic layer to determine the test result according to the write test data packet and the device information, and transmits the test result to the host computer.

4. The interface test card according to claim 2, wherein When the interface test card is an endpoint device, the programmable logic device runs the software layer to execute sending network configuration information to the board to be tested, so that the board to be tested modifies the network configuration information of the interface test card; The programmable logic device runs the software layer to execute receiving the initialization instruction output by the board to be tested and execute the initialization process; The programmable logic device runs the software layer to execute receiving the write test data packet output by the board to be tested and send the write test data packet to the service logic layer; The programmable logic device runs the service logic layer to execute feedback a read test instruction to the software layer based on the write test data packet; The programmable logic device runs the software layer to execute packing the test instruction into a read test data packet and sending it to the board to be tested.

5. The interface test card according to claim 4, characterized in that, The programmable logic device runs the service logic layer to execute storing the write test data packet.

6. The interface test card according to any one of claims 1 to 5, characterized in that The interface test card further includes: a host computer communication unit, which is disposed on the circuit board and is respectively connected to the programmable logic device and the first interface; The host computer communication unit is used to receive the reconfiguration bitstream file output by the host computer according to the board to be tested; A reconstruction management unit is provided on the static logic module, and the programmable logic device runs the reconstruction management unit to execute writing the reconstruction bitstream file to the reconfigurable logic module.

7. The interface test card according to claim 6, wherein The static logic module further includes: a controller, and the programmable logic device runs the controller to receive a test instruction transmitted by the host computer communication unit and output a reconstruction instruction to the reconstruction management unit; The interface test card further includes: a storage unit, the storage unit is provided on the circuit board and is connected to the host computer communication unit and the programmable logic device; the storage unit is used for storing the test instruction and the reconstruction bitstream file transmitted by the host computer communication unit; The programmable logic device runs the reconstruction management unit to respond to the reconstruction instruction, extract the reconstruction bitstream file in the storage unit, and write the reconstruction bitstream file to the reconfigurable logic module.

8. The interface test card according to claim 6, wherein The static logic module further includes: a PCIe control unit interface; the programmable logic device runs the PCIe control unit interface to transmit a test file between the to-be-tested board and the reconfigurable logic module.

9. An interface test system, characterized in that, Including a host computer and the interface test card according to any one of claims 1 to 8; The interface test card is respectively connected to the PCIe protocol interface of the to-be-tested board and the host computer.

10. An interface testing method, characterized in that, Applied to an interface test card, the interface test card includes: a circuit board and a programmable logic device, a first interface, and a second interface provided on the circuit board; the first interface is used for connecting to a host computer; the second interface is used for connecting to the PCIe protocol interface of the to-be-tested board; the interface test method includes: Receiving a reconstruction bitstream file output by the host computer according to the test requirements of the to-be-tested board; Forming a service logic function corresponding to the test requirements according to the reconstruction bitstream file, constituting a function test card corresponding to the test requirements, and using the function test card to test the PCIe protocol interface of the to-be-tested board.

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