Physical unclonable function circuit structure based on double delay chains

Abstract

The invention discloses a physical unclonable function circuit structure based on double delay chains. The physical unclonable function circuit structure comprises a rising edge generator, challenge generators, a delay chain D1, a delay chain D2 and an arbiter. The signal output end of the rising edge generator is respectively connected with the signal input end of the delay chain D1 and the signal input end of the delay chain D2, the signal output end of the delay chain D1 and the signal output end of the delay chain D2 are connected with the signal input end of the arbiter, the delay chain D1and the delay chain D2 are respectively formed by connecting N delay nodes, each delay node is provided with a challenge position used for adjusting delay time of input signals, and each challenge position is connected with the corresponding challenge generator which generates a random challenge value for the challenge position. The physical unclonable function circuit structure has the advantages that the same circuit structure is adopted for the delay chain D1and the delay chain D2, the same transmission signals and challenge values are input, but the two delay chains are isolated from each other without any intersection or connection, and if large fixed delay difference exists between the two delay chains, the delay difference can be balanced by setting the challenge values of all the delay nodes.

Description

[0001] technical field [0002] The invention relates to a physically unclonable function circuit structure, in particular to a physically unclonable function circuit structure based on double delay chains. Background technique [0003] With the development and popularization of information technology, all aspects of people's life are developing in the direction of networking and intelligence, and various activities in social life are increasingly realized by electronic systems. ID cards, passports are digitized, Electronic financial transactions. At the same time, smart cards, USBKeys and other circuits implementing cryptographic algorithms are becoming more and more extensive, and these cryptographic devices are increasingly carrying personal and commercial confidential information. [0004] On the other hand, the development of chip cracking technology poses a great threat to chips used in the field of information security. Physical attack belongs to the traditional ...

AI Technical Summary

Problems solved by technology

[0012] This PUF with a cross-delay chain structure has the problem that the delay deviation is not easy to balance

In the PUF design, it is expected that the two paths will go through an equal amount of delay when they reach the arbitrator, so that the random delay deviation generated in chip manufacturing can be distributed symmetrically around the zero point, but when wiring at the back end of the chip, there will always be introduced Some non-zero fixed delay differences cause the output of the arbiter to no longer reflect the randomness introduced by the process deviation

For example, when the challenge bit of a certain selector is '0' or '1', there may be a large delay difference between two parallel or cross paths, and this large delay difference is not easy to be selected by other The delay difference of the selector is offset or equalized, so...

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