44 results about "Message Signaled Interrupts" patented technology

An enhanced SCSI storage adapter with multiple queues for use by different server processors or partitions. For a non-partitioned server, the operating system (OS) owns the SCSI storage adapter, controls the adapter queues, both creation of and changes to the queues, and updates the queue table(s) in the storage adapter with queue address information, device list, message signaled interrupt (MSI) information and optional queue priorities. An OS operator can specify that one or more SCSI devices can be accessed by a specific processor or group of processors. The processor or group of processors is given an adapter queue to access the SCSI device or devices. For a partitioned server, one partition, which may be a hosting partition, owns the SCSI storage adapter, controls the adapter queues, both creation of and changes to the queues, and updates the queue table(s) in the storage adapter with queue address information, device list, message signaled interrupt (MSI) information and optional queue priorities. A system operator can assign one or more SCSI devices under a storage adapter to a partition. Each partition that has access to a SCSI device(s) under a SCSI adapter is given an adapter queue to access the device(s).

An apparatus, program product and method dynamically bind Message Signaled Interrupt (MSI) resources shared by a plurality of clients to an interrupt facility in an MSI-capable computer. In addition, management of such bindings may be implemented using a platform independent interrupt manager capable of managing multiple MSI bindings between MSI resources to an interrupt facility, and interfaced with an underlying hardware platform of a computer through platform-specific encapsulation program code.

The present invention provides a system for signaling legacy serialized interrupts within a PCI-Express environment, using message signaled interrupts. The system provides structures and methods that interface a PCI environment (106) with a PCI-Express environment (104). The present invention provides a PCI to PCI-Express bridge device (110) that is communicatively linked (112, 114) to the PCI and PCI-Express environments. The bridge device comprises a translation function (116) that is communicatively linked (120, 122) to the PCI and PCI-Express environments. A serialized interrupt is signaled from the PCI environment, and the translation function generates a message signaled interrupt within the PCI-Express environment based on that serialized interrupt.

The disclosed embodiments provide a system that validates message-signaled interrupts. During operation, the system receives a message-signaled interrupt from a requesting device. This message-signaled interrupt includes an interrupt vector that identifies an interrupt, and is accompanied by an identification tag that identifies the source of the interrupt. The system uses the interrupt vector to access a stored tag from a tracking mechanism that associates source devices with their assigned interrupt vector(s). The system then compares the identification tag and the stored tag to validate the message-signaled interrupt.

A technique for interrupt moderation allows coalescing interrupts from a device into groups to be processed as a batch by a host processor. Receive and send completions may be processed differently. When the host is interrupted for receive completions, it may check for send completions, reducing the need for interrupts related to send completions. Timers and a counter allow coalescing interrupts into a single interrupt that can be used to signal the host to process multiple completions. The technique is suitable for both dedicated interrupt line and message-signaled interrupts.

A processing method, a chip set and a controller for supporting message signaled interrupt. A memory write transaction on a PCI bus is monitored. When the address of the system memory specified in the interrupt message of the write transaction is located at a range of a reserved interrupt address, the interrupting service sequence is performed. The reserved interrupt address is located in an address of a system memory. Thus, the data to be processed and the system-specified message are written in the buffer and arranged in sequence. The problem of “write buffer latency” is resolved, and is irrelevant to the level of the PCI bus. Many system specified messages can be stored in the system memory, so that multiple system message signaled interrupts issue from different peripheral components can be processed in the same interrupt service routine.

One or more message signaled interruption requests from one or more input/output (I/O) adapters are converted to I/O adapter event notifications. Each I/O adapter event notification includes the setting of one or more specific indicators in system memory and an interruption request, the first of which results in a pending I/O adapter interruption request. While a request for an I/O adapter interruption is pending, subsequent message signaled interruption requests are converted to I/O adapter event notifications, but do not result in additional requests for I/O adapter interruptions.

A method, device, and system are disclosed. In one embodiment, the method comprises receiving a message signaled interrupt, parsing an interrupt vector from the message signaled interrupt, locating an interrupt entry associated with the interrupt vector in a table of interrupt entries, and sending information associated with the interrupt entry to a processor.

An apparatus, program product and method dynamically bind Message Signaled Interrupt (MSI) resources shared by a plurality of clients to an interrupt facility in an MSI-capable computer. In addition, management of such bindings may be implemented using a platform independent interrupt manager capable of managing multiple MSI bindings between MSI resources to an interrupt facility, and interfaced with an underlying hardware platform of a computer through platform-specific encapsulation program code.

In some embodiments, the inventions include a chip having a message signaled interrupt redirection table (MRT) that contains entries including an address field and a data field. The chip also includes translation circuitry to translate an address field and a data field of a message signaled interrupt (MSI) signal by copying contents of the address field and data field of an entry in the MRT into the address field and data field of the MSI. Other embodiments are described and claimed.

An interrupt control system is provided where a signal-line-based interrupt system can be incorporated into interrupt control using MSIs (Message Signal Interrupts). The interrupt control system includes a first PCI interface, a second PCI interface, a PCI bridge serving as a bridge between the first PCI interface and the second PCI interface, and a control circuit for controlling an interrupt signal. The PCI bridge recognizes a message signal interrupt issued from the first PCI interface to the second PCI interface and transfers the message signal interrupt to the control circuit, and the control circuit is provided with an interrupt conversion unit for converting the message signal interrupt into an interrupt signal and outputting it via a signal line.

Methods, systems, apparatuses and program products are disclosed for managing interrupt services in hypervisor and hypervisor-related environments in Message Signaled Interrupts are emulated as other type(s) of interrupt.

According to an aspect of the present invention, a method of executing a program includes receiving a MSI (message signaled interrupt). Responsively, a virtual interrupt is generated and an ISR (interrupt service routine) is invoked that handles a line-based virtual interrupt transaction. A surrogate or virtual peripheral device status may also be provided and may be associated with the virtual interrupt. A single device interrupt event may, in certain circumstances, be serviced both as a line-based interrupt and also as an MSI, or as either responsive to run-time context.

Embodiments of the present invention enable superior tradeoffs in regards to the interrupt sharing to a greater and more flexible extent than with previous implementations. Moreover, it makes possible interrupt sharing using an ISR that was not expressly designed for interrupt sharing.

A data processing system includes a processor core, a system memory, coupled to the processor core, that includes an interrupt data structure including a plurality of entries each associated with a respective one of a plurality of interrupts. An input/output (I/O) subsystem including at least one I/O host bridge and a plurality of partitionable endpoints (PEs) each having an associated PE number. The I/O host bridge, responsive to receiving a message signaled interrupt (MSI) including at least a message address, determines from the message address a system memory address of a particular entry among the plurality of entries in the interrupt data structure, accesses the particular entry, and, based upon contents of the particular entry, validates authorization of an interrupt source to issue the MSI and presents an interrupt associated with the particular entry for service.

A global interrupt number space 38 is provided for use in message signalled interrupts. Interrupt destinations 10, 12, 14, 16 are provided with pending interrupt caches 24 with either backing storage provided by global pending status memory 34 shared by all the caches or separate individual pending status memories 56. The interrupt number space may be divided into regions with programmable mapping data being used to indicate which interrupt destinations are responsible for which regions. When interrupts are migrated from one interrupt destination to another, then such programmable mapping data is updated. Pending interrupts may be flushed back to the global pending status memory 34 during the reassignment process such that this pending interrupt data may be picked up by the newly responsible interrupt destination.

The invention discloses an implementation method of an interruption conversion mechanism based on a soar platform. The method includes the steps of interruption issuing, wherein a PCIE device issues an MSI interruption request and issues a message for writing a hardware interruption number to an interruption conversion register of the soar platform according to the MSI property of the configuration space; interruption converting, wherein the PCIE device transmits the hardware interruption number to the interruption conversion register to cause shared peripheral interruption; interruption distributing, wherein the shared peripheral interruption is distributed to a central processing unit through an interruption controller; interruption processing, wherein the shared peripheral interruptionis received by the central processing unit, a shared peripheral interruption processing function is triggered, the hardware interruption number is read from the interruption conversion register, and the interruption of the PCIE device is processed. By means of the method, the conversion from the message signal interruption to the shared peripheral interruption of the PCIE device is realized, and the interruption issuing, interruption converting, interruption distributing and interruption processing of the soar platform using a GICV2 controller and supporting a PCIE bus controller are realized.

Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Apparatuses, systems, and methods are directed to securely store, transfer, and/or process data especially sensitive data sent from input devices to processors. In one embodiment, sensitive data may be packaged with at least one interrupt vector to provide a single posted write transaction initiated by an input device. The single posted write transaction may then be directly sent to a predetermined memory block allocated from a processor. In response to the single posted write transaction, a memory decoder associated with the processor may generate an emulated message signaled interrupt (MSI) signal to invoke an interrupt handler or an interrupt service routine (ISR) to service the emulated MSI using interrupt data, including the sensitive data, retrieved from the predetermined memory block. Once the sensitive data are processed by the processor, they may be removed from the processor before the processor exits the interrupt handler.