Implementation method of interruption conversion mechanism based on soar platform

Abstract

The invention discloses an implementation method of an interruption conversion mechanism based on a soar platform. The method includes the steps of interruption issuing, wherein a PCIE device issues an MSI interruption request and issues a message for writing a hardware interruption number to an interruption conversion register of the soar platform according to the MSI property of the configuration space; interruption converting, wherein the PCIE device transmits the hardware interruption number to the interruption conversion register to cause shared peripheral interruption; interruption distributing, wherein the shared peripheral interruption is distributed to a central processing unit through an interruption controller; interruption processing, wherein the shared peripheral interruptionis received by the central processing unit, a shared peripheral interruption processing function is triggered, the hardware interruption number is read from the interruption conversion register, and the interruption of the PCIE device is processed. By means of the method, the conversion from the message signal interruption to the shared peripheral interruption of the PCIE device is realized, and the interruption issuing, interruption converting, interruption distributing and interruption processing of the soar platform using a GICV2 controller and supporting a PCIE bus controller are realized.

Description

technical field [0001] The invention belongs to the technical field of processor interrupt processing, and in particular relates to an implementation method of an interrupt conversion mechanism based on a Feiteng platform. Background technique [0002] The PCIE message signal interrupt is an efficient interrupt transfer scheme supported by the general definition of the PCIE specification. Its transfer method is simple and the transfer speed is fast. In computer systems based on Phytium processors, PCIE message signal interrupts require an interrupt conversion unit in the interrupt controller to be routed and distributed. But for the processor using the GICV2 interrupt controller, because the GICV2 interrupt controller does not have an interrupt conversion unit, in the solution of the PCIE bus, only the interrupt transfer logic based on INTX can be used, which is not efficient and the design is complicated. [0003] The Phytium embedded series processors in the Phytium proce...

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Problems solved by technology

[0007] Chinese invention patent "Service request interruption router with shared arbitration unit" (application number CN201510162158.3), the invention discloses a service request interruption router, which has an interrupt control unit (ICU) and an arbitration unit, and the arbitration unit is configured by The ICUs are shared to arbitrate among Service Request Nodes (SRNs) that have their own service request interrupt signal and are mapped to the ICUs to determine which of the SRNs has the highest priority for each of the ICUs, but the above patents all Does not involve the implementation of interrupt conversion logic based on Feiteng platform

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