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Method for realizing Paillier encryption based on FPGA chip and used for federated learning

A chip and key technology, applied in the field of Paillier encryption method and FPGA chip, can solve the problems of high cost of Paillier encryption implementation scheme, increased system power consumption, and reduced CPU chip performance.

Active Publication Date: 2020-10-27
CLUSTAR TECH LO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If it is implemented with a CPU chip, it will seriously reduce the performance of the CPU chip, and the calculation efficiency is not high
If the GPU chip is used to implement, although the computing efficiency is improved, the system power consumption will be greatly increased. At the same time, because the GPU chip is expensive, the cost of the Paillier encryption implementation is relatively high.

Method used

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  • Method for realizing Paillier encryption based on FPGA chip and used for federated learning
  • Method for realizing Paillier encryption based on FPGA chip and used for federated learning
  • Method for realizing Paillier encryption based on FPGA chip and used for federated learning

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Embodiment Construction

[0030] The subject matter described herein will now be discussed with reference to example implementations. It should be understood that the discussion of these implementations is only to enable those skilled in the art to better understand and realize the subject matter described herein, and is not intended to limit the protection scope, applicability or examples set forth in the claims. Changes may be made in the function and arrangement of elements discussed without departing from the scope of the disclosure. Various examples may omit, substitute, or add various procedures or components as needed. For example, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with respect to some examples may also be combined in other examples.

[0031] As used herein, the term "comprising" and its variants represent open terms meaning "including but not limited to". The...

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Abstract

The embodiment of the invention provides a method for realizing Paillier encryption based on an FPGA chip. In the method, a data distribution module respectively distributes a plaintext data set M, akey n and a random number set r to a confusion encryption engine, a parameter calculation module and a plurality of modular exponentiation calculation engines. And the parameter calculation module determines parameters N, RR, U0 and np required by Paillier encryption according to the key n, and distributes the key n and the parameters N, RR, U0 and np to a plurality of modular exponentiation calculation engines and confusion encryption engines. And the modular exponentiation calculation engines perform parallel modular exponentiation calculation by using the random number set r, the key n andthe parameters N, RR, U0 and np. And the obtained modular exponentiation calculation result is provided to a confusion encryption engine after aggregation processing. And the confusion encryption engine performs confusion encryption by using the aggregation processing result, the key n, the parameters N, RR, U0 and np and the plaintext data set to obtain a ciphertext data set. By utilizing the method, the calculation efficiency of the Paillier encryption algorithm can be improved by utilizing the high parallel calculation characteristic of the FPGA.

Description

technical field [0001] The embodiments of this specification generally relate to the field of encryption processing, and in particular to the FPGA chip-based Paillier encryption method for federated learning and the FPGA chip. Background technique [0002] In federated learning applications, participant devices need to send local model parameter updates (for example, neural network model weights, or gradient information) to the coordinator device, so that the local model parameter updates will be learned by the coordinator. In the scenario where the reliability of the coordinator's device cannot be guaranteed, the private data information of the participant's device may be leaked. In order to ensure that the private data information of the participant device is not leaked to the coordinator device, the participant device may encrypt the private data information through the Paillier encryption algorithm. [0003] Existing Paillier encryption implementations are implemented u...

Claims

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Application Information

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IPC IPC(8): G06F21/60G06F21/76G06N20/00
CPCG06F21/602G06F21/76G06N20/00
Inventor 冯新亚王玮胡水海
Owner CLUSTAR TECH LO LTD
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