An anti-SEE system and method based on synchronizing redundant threads and coding technique

Abstract

Through the research and improvement of error-correcting codes and error-detecting codes, the anti-SEE system and method based on synchronizing redundant threads and coding technique enables this coding technique to quickly detect the SEU (single event upset) occurring in register file and meanwhile design the both-threaded mechanism of the processor into a redundant both-threaded mechanism. When the register file of a thread is found with SEU, the register data with upset error will be corrected through replacing this register file with the register file of the other redundant thread; through the comparison mechanism of synchronous execution results in the layer of redundant both-threaded instructions, the pipelined circuit is judged whether there is SET (single-event transient) error. If such error occurs, it will be quickly eliminated from the pipeline through the designed redundant thread pipeline restart mechanism. This method satisfactorily solves the two frequent and difficult problems: SMU of register file in processor and pipeline SET.

Description

technical field [0001] The invention relates to an anti-single event effect system and its realization method. Background technique [0002] In recent years, with the development of technology, the size of devices has become smaller and lower, and the operating voltage has become lower and lower, and the single event effect has become more and more serious. Especially as the clock frequency increases, the error rate caused by the SET increases linearly, even exceeding the SEU, thereby limiting the increase of the processor system clock frequency. Studies have shown that the pulse width of SET is on the order of 350 ps to 1.3 ns, so when the pulse width exceeds 1 ns, the clock frequency is limited to below 1 GHz, otherwise the SET effect may occur. On the other hand, under the ultra-deep sub-micron process, the probability of multiple bit flips in the storage circuit increases, and it is very important to design the processor to resist the single event effect. [0003] For ...

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Problems solved by technology

[0008] Therefore, this full-pipeline redundancy method requires multiple buffers, which greatly increases the hardware overhead of the system. More importantly, the storage circuit of the buffer is very sensitive to single-event flips, which will make it difficult to solve the combination The single event transient SET problem in the circuit also brings the hidden danger of single event flipping

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