Multilevel fault tolerance reinforcement satellite information processing system based on SRAM FPGA

An information processing system and satellite technology, applied in the field of satellite information processing, can solve problems such as affecting system reliability, and achieve the effect of improving reliability and performance

Active Publication Date: 2015-11-11
HARBIN INST OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0010] The purpose of the present invention is to solve the problem that when using SRAMFPGA as a satellite information processing system, due to single event flipping, latching, etc., which affect the reliability...

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  • Multilevel fault tolerance reinforcement satellite information processing system based on SRAM FPGA

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specific Embodiment approach 1

[0023] Specific implementation mode one: the following combination figure 1Illustrate this embodiment, a kind of multilevel fault-tolerant reinforcement satellite information processing system based on SRAMFPGA, it comprises:

[0024] The value range of multiple in multi-level is greater than or equal to 2;

[0025] Aiming at the SRAMFPGA process characteristics, harsh working environment in space, processing performance and reliability requirements, and considering the actual on-orbit mission requirements, design the XilinxFPGA-based Virtex-5SX series FPGA onboard data processing unit solution, which is the core unit of the onboard computer , designing a small amount of devices such as the communication interface required by the extended task of the unit can be used as an on-board computer; the unit can realize the processing tasks of C&DH, AOCS, Payload and other functions. The structure of the unit is as follows: figure 1 As shown; SRAM is static random access memory, EDAC...

specific Embodiment approach 2

[0040] Specific Embodiment 2: This embodiment further explains Embodiment 1. The verification and control module of single event effect immunity described in this embodiment includes:

[0041] The EDAC verification module is used to encode, decode, verify and correct the data in the memory, provide highly reliable storage for the LEON3 processor of the main processing module, and ensure the correct execution of the program;

[0042] EDAC verification module, the anti-fuse FPGA is connected to three external SRAMs (memory modules), and corrects and controls errors through the internal EDAC, so as to provide highly reliable memory for the LEON3 processor inside the main processing module . By using the EDAC mechanism based on Hamming coding inside the antifuse FPGA (single event effect immune verification and control module), the data verification and correction of the memory is realized, and the LEON3 processor of the main processing module provides a highly reliable external ...

specific Embodiment approach 3

[0053] Specific implementation mode three: this implementation mode further explains implementation mode one, and the main processing module described in this implementation mode includes:

[0054] The LEON3 processor IP core module is used to complete star management, task control, and internal communication and control with the main processing module;

[0055] LEON3 processor IP core: Inside the FPGA, use its logic resources to realize three LEON3 processor IP cores, and perform triple-mode redundant backup to improve reliability. A single LEON3 processor requires 4,000 LUTs, and Virtex5SX series FPGAs can have up to 149,760 LUTs, which fully meets the application requirements of simultaneously implementing three LEON3 processors;

[0056] The LEON3 processor is based on the SPARCV8 soft-core processor architecture, which itself has a multi-layer fault-tolerant mechanism to provide highly reliable computing services; the MailBox module is used to communicate among the three ...

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Abstract

The invention provides a multilevel fault tolerance reinforcement satellite information processing system based on an SRAM (Static Random Access Memory) FPGA (Field Programmable Gate Array), and relates to satellite information processing. The invention aims at solving the problems that when the SRAM FPGA is used as a satellite information processing system, the system reliability is influenced by single event upset and latch-up effects and the like, and a satellite practical task is not combined with a protection measure. The system is realized through the following modules including a memory module, a checking and control module, a memory configuration module, a state storage Flash module, an IO/BUS module, an anti-latch power supply module and a main processing module, wherein the memory module is used for data storage and program loading of a main processing module; the checking and control module is used for single event upset effect immunization; the memory configuration module is used for storing initial configuration files and remote updating configuration files; the state storage Flash module is used for realizing the data access state; the IO/BUS module is used for realizing communication and control; the anti-latch power supply module is used for system single event latch-up effect protection and power supplying to each module; and the main processing module is used for data processing and satellite event management. The multilevel fault tolerance reinforcement satellite information processing system based on the SRAM FPGA is applied to the technical field of satellites.

Description

technical field [0001] The invention relates to satellite information processing. Background technique [0002] Satellite technology is the embodiment of a country's comprehensive national strength and cutting-edge scientific and technological strength, and has an important impact on the country's military, national defense and economy. The onboard computer system is responsible for completing satellite control and data processing tasks, and is one of the core units of the satellite. In order to adapt to the harsh conditions of the space environment and the limitations of satellites in terms of volume, weight, and power consumption, the performance of the on-board computer system has always lagged far behind that of the ground-based computer system. [0003] The processor is the core component of the computer system. From the 1980s to the beginning of the 21st century, the on-board computer system processor has experienced from the switch controller, to the CPU chip represe...

Claims

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Application Information

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IPC IPC(8): G06F11/07B64G1/10
Inventor 王少军马宁崔秀海刘大同彭宇彭喜元
Owner HARBIN INST OF TECH
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