Method and device for testing single event upset in in-field programmable logic gate array

A single-event flipping and programming logic technology, which is applied in the field of single-event flipping detection, can solve the problems affecting the normal operation of FPGA devices, the high price of FPGA devices, and the improvement, and achieve the effects of simple structure, low cost, and cost reduction.

Inactive Publication Date: 2009-10-21
NAT UNIV OF DEFENSE TECH
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Problems solved by technology

[0006] At present, in the on-board signal processing platform, on the one hand, high-performance, large-scale, and high-grade FPGA devices are extremely expensive; Due to the large number of on-chip SRAM (Static Random Access Memory) used in low-priced FPGA devices, the probability of single event effects caused by space high-energy particles is greatly increased, which seriously affects the normal operation of FPGA devices in space environments

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  • Method and device for testing single event upset in in-field programmable logic gate array
  • Method and device for testing single event upset in in-field programmable logic gate array
  • Method and device for testing single event upset in in-field programmable logic gate array

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Embodiment Construction

[0029] The present invention will be further described in detail below in conjunction with specific embodiments and accompanying drawings.

[0030] Such as figure 1 As shown, inside a typical SRAM FPGA is an array composed of a configurable logic block (CLB, Configurable LogicBlock) and a switch matrix (SwitchMatrix) interlaced layout. Wherein, the CLB based on a lookup table (LUT, LookUp Table) can realize any combination of multiple input / multiple output or sequential logic circuit. The programmable interconnection point determines the connection relationship of the internal connection lines of the switch matrix, and multiple CLBs are connected together through an input / output multiplexer (IO Mux) to form a circuit required by the user. In the SRAM FPGA, the programmable bits used to configure the circuit components form a configuration bit stream, which is stored in an SRAM memory in units of configuration frames. The SRAM memory that stores the configuration bit stream i...

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Abstract

The invention discloses a method and a device for testing single event upset in in in-field programmable logic gate array, comprising the following steps: a highly reliable monitor unit which is connected with the field programmable logic gate array and used for realizing the testing flow of the single event upset is arranged; the highly reliable monitor unit executes the read back flow of the configuration memory of the field programmable logic gate array, reads the configuration frame of the field programmable logic gate array, and executes an original configuration frame which is read from a nonvolatile memory by a standard NVRAM interface; and the highly reliable monitor unit compares the read back configuration frame of the field programmable logic gate array with the original configuration frame by means of byte, when the configuration frame is wrong in comparing, namely, the configuration memory of the field programmable gate array is judged to have the single event upset. The device comprises the highly reliable monitor unit which is connected with the nonvolatile memory by a bus. The invention has the advantages of simple structural principle, high reliability, good stability, etc.

Description

technical field [0001] The invention mainly relates to the field of space instrument engineering, in particular to a detection method and device for single event flipping in a field programmable logic gate array. Background technique [0002] Cosmic space is full of various particles from the vast universe: protons, electrons, alpha particles, heavy ions, gamma rays, etc. The radiation effects caused by these particles, especially the single event effect, affect the reliability of space electronic instruments. [0003] In recent years, with the development and application of VLSI (Very Large Scale Integrated circuits) technology, Field Programmable Logic Gate Array (FPGA, Field Programmable Gate Array) has gradually replaced traditional logic circuits by virtue of its superior interface performance. It has become an important part of the on-board processing platform and has begun to be applied in aerospace engineering. [0004] With the improvement of the manufacturing proc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317G01R31/3193
Inventor 周永彬杨俊陈建云张传胜邢克飞杨建伟明德祥钟小鹏胡助理王跃科
Owner NAT UNIV OF DEFENSE TECH
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