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Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array)

A technology of clock extraction and signal synchronization, applied in the direction of automatic power control, electrical components, etc., can solve the problem that the self-synchronization method cannot be used, and achieve the effect of good noise immunity

Inactive Publication Date: 2012-07-25
NORTHEASTERN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, some modulation systems cannot use self-synchronization methods, such as SSB (Single Side Band) systems

Method used

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  • Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array)
  • Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array)
  • Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array)

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Embodiment Construction

[0049] The content of the present invention will be further described below in conjunction with the accompanying drawings.

[0050] The overall structure diagram of the system is shown in the figure 1 Shown, including AD sampling circuit and FPGA. The FPGA chip that the embodiment of the present invention adopts is the EP1C12Q240C6 of the Cyclone series of Altera Company, and described FPGA comprises the data acquisition module of realization, FIR low-pass filter module, level judgment module, edge detection module, same frequency clock generation module and Phase adjustment module. The data output pin of the AD sampling circuit is connected to the I / O port of the FPGA, and the modules inside the FPGA are generated by the Verilog HDL hardware description language in the Quartus II environment, and the data connection between the modules is realized. The signal transmission process is: AD The data collected by the sampling circuit is output to the FPGA, and the data acquisiti...

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Abstract

The invention discloses a noise adding signal synchronization clock extraction device based on an FPGA (field programmable gate array), belonging to the field of communication control. The noise adding signal synchronization clock extraction device comprises an AD (analog-digital) sampling circuit, a data acquisition module, an FIR (finite impulse response) low-pass filter module, a level judgment module, an edge detection module, a common-frequency clock generation module and a phase adjusting module, wherein the data acquisition module, the FIR (finite impulse response) low-pass filter module, the level judgment module, the edge detection module, the common-frequency clock generation module and the phase adjusting module are realized in the FPGA. According to the noise adding signal synchronization clock extraction device based on the FPGA, both data acquisition and data processing are realized by hardware, and the advantage of hardware acceleration is brought into full play; and on an FPGA platform, a verilog language is used for programming, a system is modularized, a 150-order FIR low-pass filter is designed, the rising and falling edges of a filtered signal are detected, a cycle of a synchronized signal is obtained, then the synchronized signal is extracted by a synchronizing phase, and the advantages of good noise resistance, high speed and high precision of the system are achieved.

Description

technical field [0001] The invention belongs to the technical field of communication control, and relates to a clock signal extraction technology, in particular to an FPGA-based noise signal synchronous clock extraction device. Background technique [0002] Synchronization is a very important practical problem in communication systems. In communication systems, synchronization plays a very important role. Whether the communication system can work effectively and reliably depends largely on good synchronization. Among them, bit synchronization, or symbol synchronization, is to determine the start and end moments of each symbol at the receiving end, so as to realize the correct judgment of the received information symbols. It is the most important problem among many synchronizations in digital communication. Without a bit synchronization signal, the transmitted digitally encoded information cannot be recovered normally at the communication receiving end. In recent years, th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/18
Inventor 李晶皎王泽坤李欣
Owner NORTHEASTERN UNIV
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