396 results about "Optical transistor" patented technology

A magnetic random access memory (MRAM) device has increased ΔR/R for sensing a state of a pin-dependent tunneling (SDT) device. The MRAM device includes plural transistors connected to a read line for sensing the state of the SDT device. Plural transistors lower an underlying resistance during reading, increasing ΔR/R. The plural transistors can share a source region.

Various embodiments of methods and apparatus for an amplifier with wide output voltage swing are disclosed. The amplifier may include multiple output stages, each associated with a distinct supply voltage. Each output stage may contribute current to the output of the amplifier over a range of amplifier output voltages and these ranges may overlap. Each output stage may contribute current until the amplifier output voltage reaches the supply voltage associated with that output stage. The amplifier output may be as great as the largest supply voltage minus a drop equal to Rdson for an output transistor multiplied by the output current. In a CMOS implementation, this voltage drop may be approximately 0.15V. When the amplifier output voltage is close to the supply voltage associated with an output stage, both that output stage and the output stage associated with the next highest supply voltage may contribute to the amplifier output.

An organic light emitting display comprises a display panel having a plurality of pixels, a gate drive circuit that drives scan lines and emission lines on the display panel, and a data drive circuit that drives data lines on the display panel, (n−1)th and nth pixels arranged in a row, a transistor array having a driving transistor, a sampling transistor, and a first initial transistor, and a capacitor connected between an initial voltage input terminal and the sampling transistor. A gate electrode of the first initial transistor for initializing the driving transistor of the nth pixel is connected to a scan line in the (n−1)th pixel.

Methods for operating a pixel cell include efficient transferring of photo-charges using multiple pulses to a transistor transfer gate during a charge integration period for an associated photosensor. The pixel cell can be operated with efficient transfer characteristics in either normal or high dynamic range (HDR) mode. The high dynamic range can be realized by either operating an optional HDR transistor or by fluctuating the voltage applied to a reset gate.

A current limiting circuit for a linear regulator includes an output stage transistor and a replica transistor, which have gates coupled to receive an output voltage from a linear amplifier and sources coupled to load circuitry. A drain of the output stage transistor is coupled to a V_DD supply terminal, while a drain of the replica transistor is coupled to the V_DD supply terminal through a first resistor. The output stage transistor and replica transistor are operated in saturation, such that proportional currents flow through these transistors. The voltage drop across the first resistor provides a first voltage, which is applied to a second amplifier. A reference voltage is also applied to the second amplifier. When the first voltage becomes less than the reference voltage, a feedback transistor is enabled to pull down the output voltage of the linear amplifier, thereby limiting the output current supplied to the load circuitry.

A light-emitting device according to the present invention includes a first electrode unit 9 for injecting an electron, a second electrode unit 10 for injecting a hole, and light-emitting units 11 and 12 electrically connected to the first electrode unit 9 and the second electrode unit 10 respectively, wherein the light-emitting units 11 and 12 are formed of single-crystal silicon, the light-emitting units 11 and 12 having a first surface (topside surface) and a second surface (underside surface) opposed to the first surface, plane orientation of the first and second surfaces being set to a (100) plane, thicknesses of the light-emitting units 11 and 12 in a direction orthogonal to the first and second surfaces being made extremely thin.

A differential low noise amplifier (LNA) involves two main amplifying transistors biased in saturation, and two cancel transistors biased in sub-threshold. In one example, the gates of the cancel transistors are coupled to the drains of main transistors, in a symmetrical and cross-coupled fashion. The main transistors are source degenerated. Because the gates of cancel transistors are not coupled to the differential input leads of the LNA, the input capacitance of the LNA is reduced. Noise introduced into the LNA output due to the cancel transistors being biased in the sub-threshold region is reduced because there are two stages. The first stage involves the main transistors, and the second stage involves the cancel transistors. By increasing the gain of the first stage and decreasing the gain of the second stage, overall LNA gain is maintained while reducing the noise that the sub-threshold biased transistors contribute to the LNA output.

A power control IC has a switching control circuit of a fixed on-period type which generates an output voltage from an input voltage by driving a coil by turning on and off an output transistor according to a result of comparison between a feedback voltage and a reference voltage, and a quieting circuit which forcibly turns on the output transistor by ignoring the result of comparison when, after an on-timing of the output transistor, a predetermined threshold time elapses without the next on-timing coming.

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

A shift register circuit and a shading waveform generating method are disclosed. The shift register circuit includes plural stages of shift registers. Each stage of the shift register includes an output transistor, an input unit and a gate-shading circuit. The output transistor is configured for generating an output signal of the stage of the shift register. The input unit is configured for controlling a voltage level on a gate terminal of the output transistor. The gate-shading circuit includes a first switch, a second switch and a third switch. The first switch is configured for outputting a control signal. The second switch is configured for pulling down the voltage level on the gate terminal of the output transistor according to the control signal. The third switch is configured for pulling down a level on an output terminal of the output transistor according to the control signal.

Provided is a voltage regulator which has a high speed response property in a low consumption current and is stably operable in a low output capacitance. The voltage regulator has: a differential amplifier for comparing an output of a reference voltage circuit with an output of a voltage dividing circuit and outputting a first signal; a phase compensating circuit in which a resistor and a capacitor are connected in series; a MOS transistor in which an output of the differential amplifier is inputted to a gate electrode, which is connected between a power supply and the phase compensating circuit, and in which a source is grounded; a constant current circuit connected between the MOS transistor and a ground; and an output transistor in which a second signal output from a connection point between the MOS transistor and the phase compensating circuit is inputted to a gate electrode and which is connected between the power supply and the voltage dividing circuit. A resistor side of the phase compensating circuit is connected with an output terminal of the differential amplifier and a capacitor side of the phase compensating circuit is connected with a drain electrode of the MOS transistor.

A power switching circuit according to an exemplary embodiment of the present invention includes an output transistor connected between a power supply terminal VCC and an output terminal OUT, an output controller which controls a conducting state of the output transistor according to an input signal, a sense transistor having a gate commonly connected with the output transistor, which detects an output current flowing into the output transistor, an output current detection terminal in which a detection voltage is generated according to the output current detected by the sense transistor and a short circuit detector which detects a short circuit condition of the output current detection terminal according to the detection voltage and stops the output transistor or limits the output current.

Voltage level shifting circuits are provided in which circuit devices are placed across sourcing output transistors to improve the switching speed of the low voltage to high voltage output transition. These circuit devices permit sourcing and sinking output transistors to be sized for optimal switching speed of the high voltage to low voltage output transition.

A radio frequency amplifier circuit includes: low-output transistors, each of which includes an input terminal, an output terminal, and a ground terminal, and amplifies a radio frequency signal; a harmonic processing circuit provided for each of the low-output transistors to be connected to the output terminal of the low-output transistor, and processing a secondary harmonic included in an amplified radio frequency signal, and a resistor connected to the output terminal of each of the low-output transistors. The input terminal of each of the low-output transistors is connected to an input terminal of the radio frequency amplifier circuit via an inductor, and the output terminal of each of the low-output transistors is connected to the other output terminal via the resistance and is further connected to an output terminal of the radio frequency amplifier circuit via an inductor.

A low-dropout voltage regulator apparatus includes a voltage source circuit, an error amplifier, an output transistor, a resistor-capacitor circuit, a detection circuit, and a current adjusting circuit. The voltage source circuit generates a reference voltage signal and at least one threshold voltage signal. The error amplifier receives the reference voltage signal and a feedback voltage signal to generate an output control signal. The output transistor provides an output current for the output terminal according to the output control signal. The resistor-capacitor circuit generates the feedback voltage signal using voltage dividing according to a voltage corresponding to the output current. The detection circuit compares at least one threshold voltage signal with the output voltage to generate at least one control voltage signal. The current adjusting circuit adaptively adjusts the current passing though the output transistor to decrease the transient response time according to the at least one control voltage signal.