Programmable gain amplification device and method

Abstract

An apparatus includes a plurality of gain stages connected in parallel between a first bias voltage and ground, where each gain stage includes an amplification portion and a current control portion including a first selectable signal path connected between an output of the amplification portion and a signal output, and a second selectable signal path connected between an output of the amplification portion and a signal output. And a second selectable signal path connected between the output of the amplification section and ground by a shunt device.

Description

[0001] This application is a divisional application. The application number of the original application is 201980032012.3, and the original application date is May 29, 2019. The entire content of the original application is incorporated into this application by reference.

[0002] Related Applications Cross-Application

[0003] This application is related to and claims priority to U.S. Provisional Application No. 62 / 677,352, filed on May 29, 2018, and entitled “PROGRAMMABLE GAIN AMPLIFIER APPARATUS AND METHOD”, and U.S. Non-Provisional Application No. 16 / 172,507, filed on October 26, 2018, and entitled “PROGRAMMABLE GAIN AMPLIFIER APPARATUS AND METHOD”, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure relates to a radio frequency front-end amplifier, and more particularly to a programmable gain amplifier device for adjusting the gain of the radio frequency front-end amplifier under different operating conditions. Background Art

[0005] Wireless communication systems are widely used to provide voice and data services to multiple users using various access terminals such as cellular phones, laptop computers and various multimedia devices. Such communication systems may include local area networks such as IEEE 801.11 networks, cellular phones and / or mobile broadband networks. The communication system may use one or more multiple access technologies, such as frequency division multiple access (FDMA), time division multiple access (TDMA), code division multiple access (CDMA), orthogonal frequency division multiple access (OFDMA), single carrier frequency division multiple access (SC-FDMA), etc. Mobile broadband networks can comply with a variety of standards, such as the dominant second generation (2G) technology Global System for Mobile Communications (GSM), the dominant third generation (3G) technology Universal Mobile Telecommunications System (UMTS), the dominant fourth generation (4G) technology Long Term Evolution (LTE), and the emerging fifth generation (5G) technology.

[0006] A wireless network may include a wireless device and a plurality of base stations. The wireless device may be a laptop, a mobile phone or a personal digital assistant (PDA), a media player, a gaming device, etc. The base station communicates with the wireless device via a plurality of wireless channels (e.g., downlink channels from the base station to the wireless device) coupled between the wireless device and the base station. The wireless device may send return information including channel information to the base station via a plurality of feedback channels (e.g., uplink channels from the wireless device to the base station).

[0007] The wireless device may include a transceiver coupled between an antenna and a baseband processor. The transceiver may include an amplifier and a first mixer coupled to a local oscillator. The amplifier is used to convert a radio frequency voltage signal into a radio frequency current signal. The first mixer receives the signal from the amplifier and generates a signal at an intermediate frequency suitable for the baseband processor. After being processed by the first mixer, an in-phase (I) signal having the intermediate frequency is generated and sent to the baseband processor.

[0008] The transceiver also includes a second mixer coupled to the local oscillator through a phase shifter. The phase shifter shifts the phase of the signal generated by the local oscillator by 90 degrees. The second mixer generates a quadrature (Q) signal for digital signal processing in the baseband processor.

[0009] The wireless device generally includes a front-end transconductance amplifier for converting an input RF voltage signal into an RF current signal for driving the mixer. A programmable gain amplifier is required to adjust the signal range so as to generate a suitable RF current signal for downstream devices.

[0010] It is desirable to have a high performance amplifier that exhibits good performance under a variety of operating conditions, such as high linearity, good compression performance, good gain step accuracy, low input impedance variation, etc. Summary of the invention

[0011] Preferred embodiments of the present disclosure provide a system, apparatus, and method for adjusting the gain of a radio frequency front-end amplifier under different operating conditions, generally solving or avoiding these and other problems, and generally achieving technical advantages.

[0012] According to one embodiment, an apparatus includes a plurality of gain stages connected in parallel between a first bias voltage and ground, wherein each gain stage includes an amplifying portion and a current control portion, the current control portion including a first selectable signal path connected between an output terminal of the amplifying portion and a signal output terminal, and a second selectable signal path connected between the output terminal of the amplifying portion and ground through a shunt device.

[0013] According to another embodiment, a system includes: an inverting path, wherein the inverting path includes a plurality of first gain stages connected in parallel between a first voltage and a second voltage, each first gain stage including a first amplifying part and a first current control part, the first current control part sending an output signal of the first amplifying part to a first output signal path or ground through a shunt device; and a non-inverting path, wherein the non-inverting path includes a plurality of second gain stages connected in parallel between the first voltage and the second voltage, each second gain stage including a second amplifying part and a second current control part, the second current control part sending an output signal of the second amplifying part to a second output signal path or ground through the shunt device.

[0014] According to yet another embodiment, a method includes: an amplifier receiving a radio frequency signal, wherein the amplifier includes a plurality of amplification parts connected in parallel and a plurality of current control parts respectively connected to their corresponding amplification parts; increasing the gain of the amplifier by opening a first switch of the current control part and closing a second switch of the current control part, wherein the first switch is coupled to an output terminal of the amplifier and the second switch is coupled to ground; and reducing the gain of the amplifier by closing the first switch of the current control part and opening the second switch of the current control part.

[0015] An advantage of the preferred embodiments of the present disclosure is that the gain of the RF front-end amplifier is adjusted under different operating conditions.

[0016] The above is a rather broad overview of the features and technical advantages of embodiments of the present invention, with the purpose of enabling a better understanding of the detailed description of the present invention below. Additional features and advantages of the present invention will be described below, which form the subject matter of the claims of the present invention. It will be appreciated by those skilled in the art that the disclosed concepts and specific embodiments may be easily used as a basis for modifying or designing other structures or processes for achieving the same purpose of the present invention. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present invention as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A block diagram of a mobile device according to various embodiments of the present disclosure is shown;

[0019] Figure 2 The present invention shows various embodiments of the present invention. Figure 1 A block diagram of a programmable gain amplifier is shown;

[0020] Figure 3The present invention shows various embodiments of the present invention. Figure 1 A schematic diagram of a first implementation of a programmable gain amplifier is shown;

[0021] Figure 4 The present invention shows various embodiments of the present invention. Figure 1 A schematic diagram of a second implementation of a programmable gain amplifier is shown;

[0022] Figure 5 The present invention shows various embodiments of the present invention. Figure 1 A schematic diagram of a third implementation of a programmable gain amplifier is shown;

[0023] Figure 6 The present invention shows various embodiments of the present invention. Figure 1 A schematic diagram of a fourth implementation of a programmable gain amplifier is shown;

[0024] Figure 7 The method for controlling the Figure 1 A flow chart of a method for providing a programmable gain amplifier is shown;

[0025] Figure 8 A programmable gain amplifier according to various embodiments of the present disclosure is shown; and

[0026] Fig. 9 A controller for controlling the operation of a programmable gain amplifier according to various embodiments of the present disclosure is shown.

[0027] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0028] The following is a detailed discussion of the embodiments of the present disclosure. However, it should be understood that many applicable inventive concepts provided by the present disclosure can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present invention, and do not limit the scope of the present invention.

[0029] The present disclosure will be described in conjunction with a preferred embodiment in a specific context, namely, a programmable gain amplifier for a cellular radio frequency receiver. However, the present invention can also be applied to various radio frequency devices. The embodiments will be described in detail below in conjunction with the accompanying drawings.

[0030] Figure 1A block diagram of a mobile device according to various embodiments of the present disclosure is shown. The mobile device 100 may be a laptop, a mobile phone or a personal digital assistant (PDA), a media player, a gaming device, etc. In some embodiments, the mobile device 100 may include a receiver 101, a transmitter, an antenna, and other suitable devices. Alternatively, the mobile device may include a transceiver, wherein the transmitter and the receiver are combined together and share a common circuit. For simplicity, Figure 1 Only a detailed block diagram of the receiver 101 is shown.

[0031] The receiver 101 is coupled between the antenna 102 and the baseband processor 118. Figure 1 A single antenna is shown, but the antenna 102 may include two or more antennas, for example, a main antenna and one or more backup antennas, which can be used to transmit and receive wireless communication signals. Typically, the main antenna is used to receive inbound wireless signals from the base station or to send outbound wireless signals from the mobile device to the base station. The backup antenna, as an auxiliary antenna, may not be able to receive / transmit high-performance outbound signals from the mobile device to the base station. The main function of the backup antenna is to receive diversity wireless signals. Mobile devices with two antennas are well known in the art, so they are not described here to avoid repetition.

[0032] The mobile device 100 can transmit and receive wireless signals modulated based on various standards, such as the main second generation (2nd generation, 2G) technology Global System for Mobile Communications (GSM), the main third generation (3rd generation, 3G) technology Universal Mobile Telecommunications System (UMTS), the main fourth generation (4th generation, 4G) technology Long Term Evolution (LTE) and the emerging fifth generation (5th generation, 5G) technology. In addition, the wireless signal can be modulated based on other standards, such as Worldwide Interoperability for Microwave Access (WiMAX), Wireless Local Area Network (WLAN), Ultra Wideband (UWB), etc.

[0033] The processor 118 may be any suitable baseband processor, such as a digital signal processor (DSP) chip, etc. The processor 118 is used to manage radio frequency functions and provide control software for wireless communication. The processor 118 may also be coupled to other functional units of the mobile device, such as an application processor, etc.

[0034] like Figure 1 As shown, the receiver 101 may include a plurality of filters, for example, a first filter 104, an I channel filter 111, and a Q channel filter 112. The receiver 101 may also include a plurality of gain stages, for example, an amplifier 106, an I channel amplifier 113, and a Q channel amplifier 114. In order to provide a digital signal suitable for the processor 118, as shown in FIG. Figure 1 As shown, multiple analog-to-digital (A / D) converters 115 and 116 are used. The functions of the above-mentioned filters, I channel amplifiers, Q channel amplifiers and A / D converters are well known and thus will not be described in detail here.

[0035] The amplifier 106 is used to convert the input RF voltage signal into an RF current signal to drive a mixer (e.g., mixers 107 and 108). In some embodiments, the amplifier 106 is implemented as a programmable gain amplifier. In other words, the amplifier 106 is not a fixed gain amplifier. Instead, the gain of the amplifier 106 can be dynamically adjusted according to different operating conditions.

[0036] In some embodiments, the amplifier 106 is a radio frequency complementary metal oxide semiconductor (CMOS) transconductance (gm) amplifier with programmable gain. The programmable gain can be implemented using multiple segmented CMOS transconductance gain stages, and the output ends of the multiple segmented CMOS transconductance gain stages are provided with multiple current control switches. The multiple current control switches are used to provide two output signal paths. In particular, two current control switches are connected to the output ends of each segmented CMOS transconductance gain stage. The first current control switch is coupled between the output end of the gain stage and the output end of the amplifier 106. The second current control switch is coupled between the output end of the gain stage and ground. The two current control switches are controlled by two complementary drive signals.

[0037] In operation, if the first current control switch is on and the second current control switch is off, the output current of the gain stage is sent to the output terminal of the amplifier 106. In this current control switch on / off configuration, the gain stage is configured as a conduction section. On the other hand, if the first current control switch is off and the second current control switch is on, the output current of the gain stage is grounded through a shunt capacitor. In this current control switch on / off configuration, the gain stage is configured as a disconnection section.

[0038] In operation, the output signal currents from all the on segments are summed at the output end of the amplifier 106, and the output signal currents from all the off segments are summed and connected to ground through the shunt capacitor. By controlling the amount of output current flowing through the on segments, the gain of the amplifier 106 can be adjusted accordingly. Figures 2 to 6 The detailed structure of the amplifier 106 is described. Throughout the description, the amplifier 106 is also referred to as a programmable gain amplifier.

[0039] The receiver 101 includes a signal generator 120. Figure 1 As shown, the signal generator 120 includes a local oscillator 110 and a phase shifter 109. The local oscillator 110 generates a signal at a frequency suitable for driving a mixer, and then converts the RF input signal to an intermediate frequency suitable for the processor 118. Figure 1 A first mixer 107 coupled to the local oscillator 110 is also shown. In some embodiments, the signal generated by the local oscillator 110 is a 25% duty cycle signal. After being processed by the first mixer 107, an in-phase (I) signal having the intermediate frequency is generated and sent to the processor 118.

[0040] Similarly, the second mixer 108 is coupled to the local oscillator 110 through the phase shifter 109. The phase shifter 109 shifts the phase of the signal generated by the local oscillator 110 by 90 degrees. The second mixer 108 generates a quadrature (Q) signal in the processor 118 for digital signal processing.

[0041] Throughout the description, the channel through which the in-phase signal passes is also referred to as the I channel of the receiver 101. Similarly, the channel through which the quadrature signal passes is also referred to as the Q channel of the receiver 101. Figure 1 As shown, the configurations of the I channel and the Q channel may be the same.

[0042] Figure 2 The present invention shows various embodiments of the present invention. Figure 1The block diagram of the programmable gain amplifier shown in FIG. The programmable gain amplifier 106 includes a plurality of gain stages connected in parallel. Each gain stage includes an amplification part and a current control part. Figure 2 As shown, the first gain stage includes a first amplifying part 201 and a first current controlling part 251. The first amplifying part 201 can be implemented as a CMOS transconductance amplifier. The first current controlling part 251 includes a first current controlling switch S11 and a second current controlling switch S12.

[0043] like Figure 2 As shown, the first current control switch S11 is connected between the output terminal of the first amplifying part 201 and the output terminal of the programmable gain amplifier 106. According to design requirements and different applications, the AC coupling device 210 can be placed between the first current control switch S11 and the output terminal of the programmable gain amplifier 106. In some embodiments, the AC coupling device 210 is implemented as an AC coupling capacitor.

[0044] The second current control switch S12 is connected between the output terminal of the first amplifying part 201 and the ground through a shunt device 220. In some embodiments, the shunt device 220 is implemented as a shunt capacitor.

[0045] The programmable gain amplifier 106 also includes a second gain stage and a third gain stage. Figure 2 As shown, the second gain stage includes a second amplifying part 202 and a second current control part 252. The second current control part 252 includes a third current control switch S21 and a fourth current control switch S22. The third gain stage includes a third amplifying part 203 and a third current control part 253. The third current control part 253 includes a fifth current control switch S31 and a sixth current control switch S32. The structures of the second gain stage and the third gain stage are similar to those of the first gain stage, so they are not described here to avoid repetition.

[0046] In some embodiments, Figure 2 The amplification part in is implemented as a plurality of binary weighted amplification parts connected in parallel. The plurality of binary weighted amplification parts have gain values ​​corresponding to the number of binary bits, and the range of the number of binary bits is from the least significant bit to the most significant bit. For example, according to one embodiment, the ratio of the gains of the amplification parts 201, 202 and 203 is 4:2:1.

[0047] It should be understood that the programmable gain amplifier 106 may employ any number of gain stages. For simplicity, Figure 2Three gain stages are shown in FIG. Those skilled in the art will appreciate that the number of gain stages may be changed accordingly according to different applications and design requirements.

[0048] like Figure 2 As shown, two switches (e.g., S11 and S12) are connected to the output terminal of each amplifying portion (e.g., the amplifying portion 201). More specifically, the first switch (e.g., S11) is turned on so that the output current of the amplifying portion (e.g., the amplifying portion 201) flows from the amplifying portion to the output terminal of the amplifier 106, and the second switch (e.g., S12) is turned on so that the output current of the amplifying portion (e.g., the amplifying portion 201) is grounded through the shunt device 220.

[0049] In some embodiments, Figure 2 The current control switches can be respectively implemented as multiple binary-weighted current control switches connected to their corresponding binary-weighted amplification parts. For example, current control switches S11 and S12 form a first current control part. Current control switches S21 and S22 form a second current control part. Current control switches S31 and S32 form a third current control part. These three current control parts are binary-weighted current control parts. In other words, the current control capability of each of the three current control parts is proportional to the gain of its corresponding binary-weighted amplification part. It should be understood that, as Figure 2 As shown, the actuation of the switches for controlling the current, such as S11, S21, S31, S12, S22 and S32, can be controlled by a control signal ( Figure 2 For example, if each of the switches is a transistor in a switch configuration, the control signal would be a voltage that activates the switch to the desired operating mode (open or closed).

[0050] In operation, only one of the two current control switches associated with each amplifying section can be turned on at the same time. If the first current control switch of the amplifying section is turned on, the output current of the amplifying section is added to the output terminal of the programmable gain amplifier 106, thereby increasing the amplitude of the output signal of the programmable gain amplifier 106. On the other hand, if the second current control switch of the amplifying section is turned on, the output current of the amplifying section is grounded through the shunt device 220, thereby reducing the amplitude of the output signal of the programmable gain amplifier 106. Therefore, the output current of the amplifying section can be controlled by configuring Figure 2 The on / off switching of the current-controlled switch shown dynamically adjusts the gain of the programmable gain amplifier 106 .

[0051] have Figure 2One advantage of the current control section shown is that by placing the current control switch in the output path, the current control switch only handles the output signal current. No current control switch is placed in the main high current path. This current control switch configuration allows the CMOS transistors of the amplifier section to have maximum margin, thereby having maximum linear performance and high compression.

[0052] have Figure 2 Another advantage of the current control section shown is that during the gain adjustment process, the amplification section remains operational, thereby maintaining the same input impedance or a low input impedance change at the input of the amplifier 106 .

[0053] Figure 3 The present invention shows various embodiments of the present invention. Figure 1 Schematic diagram of a first implementation of a programmable gain amplifier is shown. The programmable gain amplifier 300 includes four gain stages connected in parallel. The first gain stage includes a first amplifying portion 201 and a first current control portion 251. The second gain stage includes a second amplifying portion 202 and a second current control portion 252. The third gain stage includes a third amplifying portion 203 and a third control portion 253. The fourth gain stage includes a fourth amplifying portion 204 and a fourth current control portion 254.

[0054] The first amplifying part 201 includes a first transistor M11 and a second transistor M12 connected in series between a first bias voltage Vdd and a ground. In some embodiments, the first transistor M11 is a p-type transistor. The second transistor M12 is an n-type transistor. The gate of the first transistor M11 and the gate of the second transistor M12 are connected to the signal input terminal of the programmable gain amplifier 300 through a first input capacitor CIN1 and a second input capacitor CIN2, respectively. According to some embodiments, the first input capacitor CIN1 and the second input capacitor CIN2 are used as input DC blocking capacitors.

[0055] It should be noted that Figure 3 The first amplification section 201 used in the embodiment is selected only for demonstration purposes and is not used to limit the embodiments of the present invention to any type of amplification section. Those skilled in the art will recognize that there are many variations, alternatives and modifications. For example, the first amplification section 201 can be replaced by a plurality of amplification sections connected in parallel.

[0056] The first current control part 251 includes a first current control switch S11 and a second current control switch S12. In some embodiments, the first current control switch S11 is implemented as a first n-type transistor, such as a first metal oxide semiconductor field effect transistor (MOSFET). The second current control switch S12 is implemented as a second n-type transistor, such as a second MOSFET. In an optional embodiment, according to different applications and design requirements, the current control switches S11 and S12 can be implemented as other suitable switch elements, such as bipolar junction transistor (BJT) devices, super junction transistor (SJT) devices, bipolar transistors, etc. The first drain / source terminal of the first current control switch S11 is connected to the first drain / source terminal of the second current control switch S12, and is also connected to the common node of the first transistor M11 and the second transistor M12. The common node of the first transistor M11 and the second transistor M12 is the output end of the first amplification part 201.

[0057] The second drain / source terminal of the first current control switch S11 is connected to the output terminal of the programmable gain amplifier 300 through an output capacitor Co, and the output capacitor Co is an AC coupling capacitor. The second drain / source terminal of the second current control switch S12 is grounded through a shunt capacitor Cs. In some embodiments, the first current control switch S11 and the second current control switch S12 are implemented as n-type transistors. In some embodiments, the first drain / source terminal is a drain, and the second drain / source terminal is a source. The gate of the first current control switch S11 and the gate of the second current control switch S12 are controlled by two complementary gate drive signals.

[0058] The second amplifying section 202 includes a third transistor M21 and a fourth transistor M22 connected in series between the first bias voltage Vdd and the ground. The third amplifying section 203 includes a fifth transistor M31 and a sixth transistor M32 connected in series between the first bias voltage Vdd and the ground. The fourth amplifying section 204 includes a seventh transistor M41 and an eighth transistor M42 connected in series between the first bias voltage Vdd and the ground. The structures of the amplifying sections 202, 203 and 204 are similar to those of the first amplifying section 201, and therefore will not be discussed here to avoid repetition.

[0059] The second current control part 252 includes a third current control switch S21 and a fourth current control switch S22. The third current control part 253 includes a fifth current control switch S31 and a sixth current control switch S32. The fourth current control part 254 includes a seventh current control switch S41 and an eighth current control switch S42. The structures of the current control parts 252, 253 and 254 are similar to the structure of the first current control part 251, so they will not be discussed here to avoid repetition.

[0060] The programmable gain amplifier 300 further includes a first bias circuit, a second bias circuit and a filter circuit. The first bias circuit includes a first resistor R1, a second resistor R2, a first sensing resistor RS1 and a second sensing resistor RS2. The first resistor R1 and the second resistor R2 form a resistor divider. Figure 3 As shown, the common node of the first resistor R1 and the second resistor R2 is coupled to the gate of the p-type transistor through resistors R3 and R4. The resistor divider is used to provide a DC bias voltage for all gates of the p-type transistors M11, M21, M31 and M41. More specifically, the first bias voltage Vdd and the resistor divider are used to establish a bias point at the output end of the programmable gain amplifier 300.

[0061] In addition, the resistor divider, the first sensing resistor RS1 and the second sensing resistor RS2 are used to set the DC bias at the output end of the programmable gain amplifier 300. Figure 3 As shown, the second resistor R2 is coupled to the output capacitor Co and the shunt capacitor Cs through the sense resistors RS1 and RS2, respectively. One advantage of having this biasing configuration is that the biasing circuit provides similar DC biases for the output nodes of all gain stages, regardless of whether they are switched to the output of the amplifier 300 or to the shunt capacitors.

[0062] The second bias circuit includes a resistor R5 connected between a second bias voltage Vb and the gates of the n-type transistors (eg, n-type transistors M12, M22, M32, and M42) of the amplifying part. The second bias circuit is used to provide a DC bias for all gates of the n-type transistors.

[0063] The filter circuit is composed of the first resistor R1, the second resistor R2, the third resistor R3 and the capacitor CF. The common node between R3 and R4 is coupled to the AC ground through the capacitor CF. The capacitor CF provides a low-pass filtering function together with the resistors R1, R2 and R3 for filtering unwanted noise from the n-type transistor associated with the amplification section. The resistor R4 is used to provide isolation between the filter circuit and the p-type transistor.

[0064] In some embodiments, the first resistor R1 is a 140Kohm resistor. The second resistor R2 is a 125Kohm resistor. The third resistor R3 is a 90Kohm resistor. The fourth resistor R4 is a 5Kohm resistor. The fifth resistor R5 is a 100Kohm resistor. The first sensing resistor RS1 is a 3Kohm resistor. The second sensing resistor RS2 is a 3Kohm resistor. The resistors R1, R2, R3, R4 and R4 can be implemented as conventional resistors. Alternatively, the resistors R1, R2, R3, R4 and R4 can be composed of transistors. As is well known, transistors can be used as resistors.

[0065] It should be noted that the above resistance values ​​are selected for illustration purposes only and are not intended to limit the embodiments of the present disclosure to any particular resistance value.

[0066] In some embodiments, the shunt capacitor Cs is a 10 pF capacitor. The capacitor Co is a 10 pF capacitor. The first input capacitor CIN1 is a 3 pF capacitor. The second input capacitor CIN2 is a 3 pF capacitor. The capacitance of the filter capacitor CF is in the range of about 5 pF to about 10 pF.

[0067] It should be noted that the above capacitance values ​​are selected for illustration purposes only and are not intended to limit the embodiments of the present disclosure to any specific capacitance values.

[0068] In some embodiments, the first bias voltage Vdd is about 1.2V, and the second bias voltage Vb is about 300mV. It should be noted that the above bias voltages are selected for illustrative purposes only, and do not limit the embodiments of the present disclosure to any specific bias voltages. Both the first bias voltage and the second bias voltage may vary according to different manufacturing processes.

[0069] have Figure 3 One advantage of the bias circuit shown is that the bias circuit is minimized by implementing a single bias network shared by all segments, thereby reducing the die area and cost of the programmable gain amplifier 300.

[0070] In addition, the current control switch in series with the shunt capacitor provides a low impedance path for the current output signal of each disconnected segment. This low impedance path minimizes the voltage swing at the output of each disconnected segment. If the voltage swing of the disconnected segment output node is small, the undesired parasitic signal coupled by the amplifier output of the turn-off switch is minimized, resulting in a higher gain step accuracy.

[0071] Figure 4 The present invention shows various embodiments of the present invention. Figure 1 Schematic diagram of a second implementation of a programmable gain amplifier 400. Figure 3 Similar to the example shown, except Figure 3 The resistor divider shown is replaced outside of the feedback amplifier 401 .

[0072] The non-inverting input terminal of the feedback amplifier 401 is connected to the common node of the two sensing resistors RS1 and RS2. The inverting input terminal of the feedback amplifier 401 is connected to a predetermined voltage reference, which sets the DC bias of the amplification part. In some embodiments, the predetermined voltage reference is equal to half of the bias voltage Vdd. Figure 4 The bias circuit shown results in less bias voltage variation under different manufacturing processes and operating conditions. The filter formed by R3 and CF can form a pole for better loop compensation.

[0073] Figure 5 The present invention shows various embodiments of the present invention. Figure 1 Schematic diagram of a third implementation of a programmable gain amplifier is shown. The programmable gain amplifier 500 is Figure 3 The differential implementation of the programmable gain amplifier 300 is shown in FIG. Figure 5 As shown, the programmable gain amplifier 500 includes a non-inverting path 502 and an inverting path 504. The non-inverting path 502 and the inverting path 504 both have Figure 3 The structure shown is similar to that shown in FIG. 5 , but the non-inverting path 502 and the inverting path 504 may share the shunt capacitor Cs.

[0074] like Figure 5 As shown, the input signal of the programmable gain amplifier 500 is not directly applied to the input end of the non-inverting path 502. Instead, the input signal passes through the inverter 501. After passing through the inverter 501, the input signal is converted into a signal with a 180-degree phase shift relative to its input, and is fed into the input end of the non-inverting path 502. The input signal of the programmable gain amplifier 500 is directly applied to the input end of the inverting path 504.

[0075] like Figure 5 As shown, the non-inverting path 502 includes a plurality of first gain stages (eg, Figure 5 201 to 204 and 251 to 254 in the upper half of ). Each first gain stage includes a first amplification section (eg, Figure 5 201 in the upper half) and the first current control portion (eg, Figure 5 251 in the upper part of ).

[0076] The first current control part of the non-inverting path 502 is used to send the output signal of the first amplifying part to the first output signal path or ground through a shunt device. In particular, when the current control switch S11 is turned on, the output signal of the first amplifying part 201 is sent to the first output signal path. The first output signal path is located between the output terminal of the first amplifying part 201 and the first output terminal OUTP. On the other hand, when the current control switch S12 is turned on, the output signal of the first amplifying part 201 is grounded through a low-impedance shunt capacitor Cs. It should be noted that the current control switches S11 and S12 are controlled by two complementary gate drive signals.

[0077] In some embodiments, the amplification part of the non-inverting path 502 is implemented as a plurality of binary-weighted amplification parts connected in parallel. The plurality of binary-weighted amplification parts have gain values ​​corresponding to a predetermined number of binary bits, and the range of the binary bit number is from the least significant bit to the most significant bit. For example, the ratio of the gains of the amplification parts 201, 202, 203 and 204 of the non-inverting path 502 is 8:4:2:1.

[0078] In some embodiments, the non-inverting path 502 further includes a plurality of binary-weighted current control sections respectively connected to the corresponding binary-weighted amplifying sections thereof. More specifically, each of the plurality of binary-weighted current control sections has a current control capability proportional to the gain of the corresponding binary-weighted amplifying section.

[0079] The inverting path 504 includes a plurality of second gain stages (eg, Figure 5 201 to 204 and 251 to 254 in the lower half of ). Each second gain stage includes a second amplification section (e.g., Figure 5 201 in the lower half of the second current control section (eg, Figure 5 251 in the lower part of ).

[0080] The second current control part is used to send the output signal of the second amplification part to the second output signal path or to the ground through the current shunt device Cs. In particular, when the current control switch S11 ( Figure 5 When the current control switch S12 ( Figure 5 When the lower half of the amplifier is turned on, the output signal of the second amplifying part is grounded through the low impedance shunt capacitor Cs.

[0081] It should be noted that the inverting path 504 may include a plurality of binary-weighted amplification parts and a binary-weighted current control part. The structure of the binary-weighted amplification part and the binary-weighted current control part of the inverting path 504 is similar to that of the non-inverting path 502, so it will not be described again to avoid repetition.

[0082] Figure 6 The present invention shows various embodiments of the present invention. Figure 1 600 is a schematic diagram of a fourth implementation of a programmable gain amplifier. The schematic diagram of the programmable gain amplifier 600 is similar to that of Figure 3 The first bias circuit includes R11 and R12. The first bias circuit is used to set the DC bias of the p-type transistor M11.

[0083] The second bias circuit includes R21 and R22. The second bias circuit is used to set the DC bias of the p-type transistor M21. The third bias circuit includes R31 and R32. The third bias circuit is used to set the DC bias of the p-type transistor M31. The fourth bias circuit includes R41 and R42. The fourth bias circuit is used to set the DC bias of the p-type transistor M41.

[0084] Figure 7 The method for controlling the Figure 1 A flow chart of a method for providing a programmable gain amplifier is shown. Figure 7 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize that there are many variations, alternatives, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 7 The various steps shown.

[0085] Continue to refer Figure 1 and Figure 2, the receiver 101 includes a programmable gain amplifier 106. The programmable gain amplifier 106 includes a plurality of gain stages connected in parallel between a first bias voltage and ground. In some embodiments, each gain stage includes an amplification part and a current control part.

[0086] The amplifying part includes a first transistor and a second transistor connected in series between the first bias voltage and ground. The first transistor is a p-type transistor. The second transistor is an n-type transistor. The gate of the first transistor and the gate of the second transistor are respectively used to receive an input signal through a first input capacitor and a second input capacitor.

[0087] The current control part includes a first signal path and a second signal path. The first signal path is connected between the output terminal of the amplifying part and the signal output terminal of the programmable gain amplifier 106. The second signal path is connected between the output terminal of the amplifying part and the ground through a shunt capacitor.

[0088] The first signal path includes a first current-controlled switch connected between the output terminal of the amplifying part and the signal output terminal of the programmable gain amplifier 106. An AC coupling capacitor may be provided in the first signal path.

[0089] The second signal path includes a second current control switch connected between the output terminal of the amplifying part and ground through a shunt capacitor. The gate of the first current control switch and the gate of the second current control switch are used to receive two complementary gate drive signals.

[0090] In step 702, an amplifier is used to receive a radio frequency signal. In some embodiments, the amplifier is a transconductance amplifier, including a plurality of amplification parts connected in parallel and a plurality of current control parts respectively connected to the corresponding amplification parts.

[0091] In step 704, the gain of the amplifier is increased by opening a first switch of a current control part and closing a second switch of the current control part. The first switch is coupled between an output terminal of an amplifying part and an output terminal of the amplifier. The second switch is coupled between the output terminal of the amplifying part and ground.

[0092] In step 706, the gain of the amplifier is reduced by closing the first switch of the current control section and opening the second switch of the current control section.

[0093] Figure 8A programmable gain amplifier according to various embodiments of the present disclosure is shown. The programmable gain amplifier 802 is a front-end transconductance amplifier used in the signal path of a radio frequency integrated circuit. The programmable gain amplifier 802 is used to convert an RF voltage signal IN into an RF current signal OUT to drive a passive mixer and a transimpedance amplifier. The programmable gain amplifier 802 needs to have an adjustable gain to accommodate a wide range of RF input voltage signals.

[0094] In order to have an adjustable gain, the programmable gain amplifier 802 can be implemented as Figure 3 The programmable gain amplifier 300 shown, Figure 4 The programmable gain amplifier 400 shown, Figure 5 The programmable gain amplifier 500 shown in FIG. Figure 6 The programmable gain amplifier 600 shown, or any combination thereof.

[0095] In some embodiments, Figure 1 As shown, the programmable gain amplifier 802 can be used in a receiver. In an optional embodiment, the programmable gain amplifier 802 can be used in a transmitter that drives an antenna. In addition, the programmable gain amplifier 802 can be used in various wireless communication systems, such as mobile phones, base stations, etc.

[0096] Fig. 9 902 is used to control the operation of the programmable gain amplifier (eg, Figure 2 The controller 902 may be implemented as any suitable control device, such as a digital signal processor (DSP) chip, a microcontroller, a control unit of a central processing unit, etc.

[0097] like Fig. 9 As shown, the controller 902 has three input terminals. The first input terminal is used to receive the RF voltage signal IN. The second input terminal is used to receive the RF current signal OUT. The third input terminal is used to receive a predetermined system control signal CONTROL. Based on the received signals IN, OUT and CONTROL, the controller 902 can generate a plurality of gate drive signals for controlling the on / off of switches S11, S12, S21, S22, S31 and S32.

[0098] Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

[0099] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, components, methods, and steps described in the specification. A person skilled in the art can easily understand from the present invention that existing or to-be-developed processes, machines, manufactures, compositions of matter, components, methods, or steps that have substantially the same functions as the corresponding embodiments described herein or can achieve substantially the same results as the embodiments described herein can be used in accordance with the present invention. Accordingly, the scope of the appended claims includes such processes, machines, products, compositions of matter, modes, methods, and steps.

Claims

1. A programmable gain amplifier, characterized in that: include: A plurality of selectable gain stages are connected in parallel between a first bias voltage and ground, wherein: Each selectable gain stage includes: Zoom in on the part; a first selectable signal path connected between the output of the amplification section and the signal output; and A second selectable signal path is connected between the output of the amplifying portion and ground through a shunt device.

2. The programmable gain amplifier according to claim 1, characterized in that: The enlarged part includes: A first transistor and a second transistor are connected in series between the first bias voltage and ground.

3. The programmable gain amplifier according to any one of claims 1 to 2, characterized in that: The first transistor is a p-type transistor; and The second transistor is an n-type transistor, wherein a gate of the first transistor and a gate of the second transistor receive input signals through a first input capacitor and a second input capacitor, respectively.

4. The programmable gain amplifier according to any one of claims 1 to 3, characterized in that: The first selectable signal path includes a first current-controlled switch, and the second selectable signal path includes a second current-controlled switch, wherein A first drain / source terminal of the first current control switch is connected to the output terminal of the amplifying part, and a second drain / source terminal of the first current control switch is connected to the signal output terminal; as well as A first drain / source terminal of the second current control switch is connected to the output terminal of the amplifying part, and a second drain / source terminal of the second current control switch is grounded via a shunt capacitor.

5. The programmable gain amplifier according to any one of claims 1 to 4, characterized in that: The gate of the first current control switch and the gate of the second current control switch are controlled by two complementary gate drive signals.

6. The programmable gain amplifier according to any one of claims 1 to 5, characterized in that: Also includes: A bias circuit for setting a DC bias point at the signal output terminal, wherein the bias circuit comprises a resistor divider, a first sensing resistor and a second sensing resistor, wherein the first sensing resistor being connected to the first selectable signal path; the second sensing resistor being connected to the second selectable signal path; as well as The resistor divider is connected between the first bias voltage and a common node of the first sense resistor and the second sense resistor.

7. The programmable gain amplifier according to any one of claims 1 to 6, characterized in that: Also includes: A bias resistor is connected between a second bias voltage and the amplifying portion, wherein the second bias voltage and the bias resistor provide a bias current for the amplifying portion.

8. A programmable gain amplifier, characterized in that: include: an inverting path, comprising a plurality of first gain stages connected in parallel between a first voltage and a second voltage, wherein each first gain stage comprises a first amplifying portion and a first current controlling portion, the first current controlling portion sending an output signal of the first amplifying portion to a first output signal path or ground via a current dividing device; and A non-inverting path includes a plurality of second gain stages connected in parallel between the first voltage and the second voltage, wherein each second gain stage includes a second amplifying part and a second current controlling part, and the second current controlling part sends the output signal of the second amplifying part to a second output signal path or ground through the shunt device.

9. The programmable gain amplifier according to claim 8, characterized in that: The second voltage is a ground voltage potential; and The first voltage is a voltage potential greater than the second voltage.

10. The programmable gain amplifier according to any one of claims 8 and 9, characterized in that: Also includes: a bias circuit for setting a first bias point at a signal output end of the first output signal path and a second bias point at a signal output end of the second output signal path, wherein the bias circuit comprises a first resistor divider, a second resistor divider, a first sensing resistor, a second sensing resistor, a third sensing resistor, and a fourth sensing resistor; The first sensing resistor and the second sensing resistor are connected to the first output signal path and the current shunt device, respectively; The third sensing resistor and the fourth sensing resistor are connected to the second output signal path and the current shunting device, respectively; The first resistor divider is connected between a first bias voltage and a common node of the first sense resistor and the second sense resistor; and The second resistor divider is connected between the first bias voltage and a common node of the third sense resistor and the fourth sense resistor.

11. The programmable gain amplifier according to any one of claims 8 to 10, characterized in that: Also includes: An inverter is connected between an input signal terminal and the non-inverting path, wherein the inverting path is directly connected to the input signal terminal.

12. The programmable gain amplifier according to any one of claims 8 to 11, characterized in that: The inverting path includes a plurality of binary-weighted first amplifying parts connected in parallel, wherein the plurality of binary-weighted first amplifying parts have gain values ​​corresponding to a predetermined number of binary bits ranging from a least significant bit to a most significant bit.

13. The programmable gain amplifier according to any one of claims 8 to 12, characterized in that: The inverting path includes a plurality of binary-weighted first current control parts, wherein the plurality of binary-weighted first current control parts are respectively connected to their corresponding binary-weighted first amplification parts, and each of the plurality of binary-weighted first current control parts has a current control capability that is proportional to the gain of the corresponding binary-weighted first amplification part.

14. A mobile device, characterized in that: include: A programmable gain amplifier according to any one of claims 1 to 13, and an in-phase / quadrature mixer, wherein the programmable gain amplifier is coupled to the in-phase / quadrature mixer.

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