Secondary extension structure of silicon carbide

Abstract

The present invention discloses a carborundum secondary epitaxy material structure used for carborundum preparation comprising of: a carborundum single crystal substrate, a first homoepitaxy layer on surface of substrate, a secondary epitaxy material on surface of first homoepitaxy which comprises of p-type carborundum buffer layer, n-type carborundum active layer and unintentional doped intrinsic carborundum layer. Corresponding to MESFET (metal mosfet) with common structure, the MESFET fabricated by secondary epitaxy type has merits of small source-drain resistance, large ohm interface and uniform electric field distribution of working field in MESFET, can enhance transconductance, improve working voltage and power of appliance, and at the same time, the technique of preparation is simplified and the stability of appliance is ensured.

Description

technical field [0001] The invention relates to a silicon carbide secondary epitaxy structure, in particular to a silicon carbide secondary epitaxy structure which can shorten the process flow and improve the performance of silicon carbide devices. Background technique [0002] Silicon carbide material is one of the representative materials of the third-generation semiconductor. Compared with the first-generation semiconductor element material represented by silicon and the second-generation compound semiconductor material represented by gallium arsenide, silicon carbide has a wide band gap and high critical mass. Breakdown electric field, high carrier saturation drift velocity, high thermal conductivity and other characteristics. Specifically, taking 4H-SiC as an example, at 300K (27°C), the forbidden band width of silicon carbide is 3.2eV, which is much wider than 1.12eV of silicon and 1.43eV of gallium arsenide. In this way, the operating temperature of silicon carbide m...

AI Technical Summary

Problems solved by technology

[0004] 1. The depth of ion implantation in silicon carbide is shallow, the activation rate of implanted ions is very low, and the implantation efficiency is low, which makes it difficult to apply this common and important process in semiconductor preparation

[0005] 2. There is no practical wet etching process in the device processing technology, only dry etching process can be used

[0007] 1. Dry etching will cause damage, resulting in a decrease in carrier mobility that is critical to device performance, a decrease in crystal quality, and degradation of material properties, ultimately

Images