2 results about "Strain engineering" patented technology

Technologies for strain engineering in gate-all-around (GAA) field-effect transistors (FETs) are disclosed. In an illustrative embodiment, the source / drain contacts for N-type metal-oxide-semiconductor (NMOS) FETs extend deeper into the source / drain regions than the source / drain contacts for P-type metal-oxide-semiconductor (PMOS) FETs. The source / drain contacts for the NMOS FETs may cause a tensile strain in the channel of the NMOS FETs, while the source / drain region of the PMOS FETS may cause a compressive strain in the channel of the PMOS FETs. The tensile and compressive strains on the NMOS and PMOS channels, respectively, can increase the speed of the NMOS and PMOS transistors.

This invention discloses a heteroepitaxial composite substrate with in-situ thermo-mechanical coupling suppression characteristics and its fabrication method. The substrate is prepared by continuously growing lattice-coherent stress-relieving, compositional equilibrium, and pre-stress compensation sections on a single-crystal silicon support substrate using vapor phase epitaxy. Through the synergistic effect of a step-decreasing germanium composition and a pulsed fluctuating carbon composition, an asymmetric strain field is constructed in-situ within the single-crystal lattice. Cyclic thermal annealing during fabrication enables deep pinning of penetrating dislocations and precise arrangement of the micro-strain trap array. This invention not only solves the inherent lattice constant mismatch problem in heteroepitaxial growth but also ensures extremely high single-crystal quality and structural integrity of the top epitaxial layer through in-situ strain engineering, achieving dynamic stress balance within the material system over a wide temperature range.