Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device which comprises a substrate, a shallow trench isolation, a channel region, a gate stack and source-drain regions. The STI is embedded into the substrate and provided with at least one open region; the channel region is arranged in the open region; the gate stack comprises a gate medium layer and a gate electrode layer, and is located above the channel region; the source-drain regions are arranged on two sides of the channel region, and each source-drain region comprises a stress layer used for providing strain for the channel region. A packing layer is arranged between the STI and each stress layer and serves as a crystal seed layer of the stress layer; a packing layer and a cushion oxidation layer are arranged between the substrate and the STI. According to the semiconductor device, due to the fact that the packing layer is inserted between the STI and the stress layer of each source-drain region and serves as the crystal seed layer or a nucleating layer for epitaxial growth, the STI fringe effect in source-drain strain engineering is eliminated, a gap between the STI and the stress layer of each source-drain region is also eliminated, reduction of stress of the source-drain strain on channels is prevented, the carrier mobility of MOS devices is improved, and therefore the drive capability of the devices is improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a semiconductor device structure with an improved epitaxial edge and a manufacturing method thereof. Background technique [0002] The current method of reducing cost by reducing the feature size alone has encountered a bottleneck, especially when the feature size drops below 150nm, many physical parameters cannot be scaled, such as silicon band gap Eg, Fermi potential The interface state and oxide layer charge Qox, thermoelectric potential Vt and self-built potential of pn junction, etc., will affect the performance of scaled down devices. [0003] In order to further improve device performance, stress is introduced into the MOSFET channel region to improve carrier mobility. For example, on a wafer with a crystal plane of (100), the crystal orientation of the channel region is <110>. In PMOS, the stress along the longitudinal axis (along the source-drain direction) n...

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Problems solved by technology

Similar to PMOS, SiC will also become thinner at the STI edge of NMOS, reducing the drive capability

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