Semiconductor device and manufacturing method thereof

A semiconductor and device technology, which is applied in the field of improving the structure of epitaxial edge semiconductor devices and its manufacturing, can solve problems such as reducing driving capability, and achieve the effects of preventing stress reduction, eliminating voids, and eliminating STI edge effects.

Active Publication Date: 2012-08-01
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Similar to PMOS, SiC will also become thinner at the STI edge of NMOS, reducing the drive capability

Method used

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  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof
  • Semiconductor device and manufacturing method thereof

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Embodiment Construction

[0024] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower", "thick", "thin" and the like used in this application can be used for Modify various device structures. These modifications do not imply a spatial, sequential or hierarchical relationship of the modified device structures unless specifically stated.

[0025] 7 to 11 show schematic cross-sectional views of epitaxially growing SiGe on source and drain regions in the prior art.

[0026] First, as shown in FIG. 7, shallow trenches are formed by etching. A pad oxide layer 20 is deposited on the substrate 10, and shallow trenches are formed by conventional mask exposure and etching. Wherein, the substrate 10 may be bulk silicon or...

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Abstract

The invention provides a semiconductor device, comprising: a substrate; a shallow trench isolation means embedded in the substrate, and forming at least one open area; a channel region positioned in the open area; a gate stack, positioned on top of the channel region, comprising a gate dielectric layer and a gate electrode layer; a source-drain area, positioned on the two sides of the channel region, comprising a stress layer for providing a strain to the channel region. There is a liner between the shallow trench isolation means and the stress layer. By inserting a liner of a material same or similar to that of the stress layer of the source-drain area between the STI and the stress layer of the source-drain area, wherein the liner acts asa crystal seed layer or a nucleating layer for epitaxial growth an edge effect of STI during the source-drain area process is eliminated, that is a gap between the STI and the stress layer of the source-drain area is eliminated, the reduction of the channel stress caused by the source-drain area is prevented, and a mobility of the current carriers of the metal-oxide semiconductor (MOS) device is improved, thus improving a driving capability of the device.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a semiconductor device structure with an improved epitaxial edge and a manufacturing method thereof. Background technique [0002] The current method of reducing cost by reducing the feature size alone has encountered a bottleneck, especially when the feature size drops below 150nm, many physical parameters cannot be scaled, such as silicon band gap Eg, Fermi potential The interface state and oxide layer charge Qox, thermoelectric potential Vt and self-built potential of pn junction, etc., will affect the performance of scaled down devices. [0003] In order to further improve device performance, stress is introduced into the MOSFET channel region to improve carrier mobility. For example, on a wafer with a crystal plane of (100), the crystal orientation of the channel region is <110>. In PMOS, the stress along the longitudinal axis (along the source-drain direction) n...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/16H01L29/06H01L29/41H01L21/762H01L21/336H01L21/28
CPCH01L21/76224H01L29/7848H01L29/66636H01L29/7846
Inventor 王桂磊尹海洲
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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