High-voltage NLDMOS (N-type laterally diffused metal oxide semiconductor) structure for electrostatic protection

Abstract

The invention discloses a high-voltage NLDMOS (N-type laterally diffused metal oxide semiconductor) structure for electrostatic protection. The high-voltage NLDMOS structure comprises an NLDMOS formed in an N-type buried layer above a silicon substrate. The NLDMOS is arranged to be a multi-finger structure. A source region between two drain regions is a joint source region. N-type active regions and P-type active regions are arranged at intervals along the length direction in active regions of the drain regions. The P-type active regions are inserted into the joint source region and embedded in the N-type active regions. The N-type active regions in the source region are separated respectively by the P-type active regions. The P-type active regions and the N-type active regions are arranged at intervals along the length direction. All drain electrodes are connected to an ESD (electro-static discharge) access end. All source electrodes are connected to the ground. All grid electrodes are connected to a signal end. By changing the width of a diffused region P+, close to the grid electrodes, on the source region, the high-voltage NLDMOS structure can effectively adjust trigger current and snapback voltage. By the high-voltage NLDMOS structure applied to high-voltage electrostatic protection, locking-resisting capability of an LDMOS (laterally diffused metal oxide semiconductor) can be effectively improved, and electrostatic protection capability of the LDMOS can be ensured not to be affected.

Description

technical field [0001] The invention relates to an electrostatic protection structure of a semiconductor device, in particular to a high-voltage NLDMOS structure for electrostatic protection. Background technique [0002] The existing high-voltage NLDMOS (N-type laterally diffused metal field effect transistor) structure for electrostatic protection is as follows: figure 1 As shown, under the occurrence of static electricity, after the ESD (electrostatic discharge) positive charge enters the drain from the input and output pads, the potential of the N- diffusion region will be raised, and an avalanche breakdown will occur; the breakdown current passes through the P+ diffusion in the P well The area is drawn out, and the potential of the P well is raised at the same time, causing the parasitic transistor to be turned on. The parasitic triode is a lateral triode composed of an N- diffusion region of the drain, an N+ diffusion region of the source and a high-voltage P well und...

AI Technical Summary

Problems solved by technology

but, figure 2 The low turn-on current of the structure is detrimental to the anti-latch-up effect

Images