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Lateral power device with mixed conduction mode and method of making same

A lateral power device and mode technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electro-solid devices, etc., can solve the problems of low on-state voltage drop, reduced device loss characteristics, large turn-off loss, etc. Manufacturing difficulty, reducing turn-off loss, and improving the effect of breakdown voltage

Active Publication Date: 2020-05-01
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the LIGBT device is turned on, due to the conductance modulation effect in the drift region, a low turn-on voltage drop can be obtained, but when it is turned off, due to the existence of a large number of unbalanced carriers stored in the drift region, the turn-off time is long, Large turn-off loss
At the same time, due to the existence of the PN junction in the collector area of ​​the device, when the device is conducting forward, in the low collector voltage region, and at the same current density, the conduction voltage drop of LIGBT is larger than that of LDMOS devices, which is not conducive to the reduction of device loss characteristics. Small

Method used

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  • Lateral power device with mixed conduction mode and method of making same
  • Lateral power device with mixed conduction mode and method of making same
  • Lateral power device with mixed conduction mode and method of making same

Examples

Experimental program
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Effect test

Embodiment 1

[0041] A transverse power device with mixed conduction mode, the cell structure and the cross-sectional view along line AA’ are as follows: figure 2 and image 3 As shown, it includes a P-type substrate 1, a buried oxide layer 2, and an N-type drift region 3 arranged in order from bottom to top; one end of the N-type drift region 3 is provided with a P-type base region 4, and the other end is provided with an N-type Buffer area 8; the P-type base region 4 is provided with an N-type source region 5 and a P-type contact region 6 above the interior, and the N-type buffer region 8 is provided with a P-type collector region 9 above the interior; the P-type contact There is an emitter 10 above the region 6 and part of the N-type source region 5; a part of the upper surface of the P-type collector region 9 has a collector 12; a gate dielectric layer 7 is also provided above the P-type base region 4. There is a gate electrode 11 above the dielectric layer 7. The length of the gate stru...

Embodiment 2

[0050] Such as Figure 4 with Figure 5 As shown, the difference between this embodiment and Embodiment 1 is that there is an N-type layer 18 between the N-type strip 13, P-type strip 14 and the P-type RESURF layer 16, and the concentration of the N-type layer 18 is greater than The concentration of the N-type drift region 3. Compared with Embodiment 1, this embodiment can further improve the current conduction capability of the lateral MOSFET.

Embodiment 3

[0052] Such as Image 6 As shown, the difference between this embodiment and Embodiment 1 is that the P-type RESURF layer 16 is composed of a first sub-region 161, a second sub-region 162, and a third sub-region 163 whose concentrations decrease from left to right. Compared with Embodiment 1, this embodiment can further increase the breakdown voltage of the device.

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PUM

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Abstract

The invention provides a lateral power device with a mixed conduction mode and a preparation method thereof, comprising a P-type substrate, a buried oxide layer, an N-type drift region, a P-type base region, an N-type buffer region, an N-type source region, a P-type Contact region, P-type collector region, emitter, collector, gate dielectric layer, gate electrode, N-type drift region surface has N-type strips and P-type strips, N-type strips and P-type strips are perpendicular to the device drift region surface The channel length direction is arranged alternately, and there is a P-type RESURF layer in the drift region under the N-type strip and P-type strip; there is a dielectric groove structure between the N-type strip, P-type strip, and P-type RESURF layer and the N-type buffer zone; The concentration of N-type strips and P-type strips is greater than the concentration of N-type drift regions; the depth of the dielectric groove structure is not less than the depth of N-type strips, P-type strips and P-type collector regions; the invention realizes surface SJ-LDMOS and LIGBT The mixed conduction can obtain lower turn-on voltage drop, higher withstand voltage, faster switching speed, lower turn-off loss, and eliminate the snapback effect, greatly improving device performance.

Description

Technical field [0001] The invention belongs to the technical field of power semiconductor devices, and particularly relates to a lateral power semiconductor device with a mixed conduction mode and a preparation method thereof. Background technique [0002] Lateral Insulated Gate Bipolar Transistor (LIGBT) is a lateral power device that combines the advantages of both lateral power MOSFET and bipolar transistor. It also has the characteristics of high input impedance and reduced conduction voltage. , Is widely used in various power integrated circuits. Compared with traditional devices based on bulk silicon technology, devices manufactured using SOI technology have many advantages such as fast speed, low power consumption, high integration density, strong latch-up resistance, low cost, and good radiation resistance. Therefore, the LIGBT device based on SOI material also has the advantages of good insulation performance, low substrate leakage current, small parasitic capacitance ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/739H01L29/06H01L27/12H01L21/84
CPCH01L21/84H01L27/1207H01L29/0615H01L29/0634H01L29/0649H01L29/7394
Inventor 张金平崔晓楠刘竞秀李泽宏任敏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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