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Lateral power device with mixed conduction mode and preparation method thereof

A technology of lateral power devices and modes, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of large turn-off loss, reduced device loss characteristics, low conduction voltage drop, etc., and achieve improved The effects of breakdown voltage, reduced turn-off loss, and increased manufacturing difficulty

Active Publication Date: 2018-03-16
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the LIGBT device is turned on, due to the conductance modulation effect in the drift region, a low turn-on voltage drop can be obtained, but when it is turned off, due to the existence of a large number of unbalanced carriers stored in the drift region, the turn-off time is long, Large turn-off loss
At the same time, due to the existence of the PN junction in the collector area of ​​the device, when the device is conducting forward, in the low collector voltage region, and at the same current density, the conduction voltage drop of LIGBT is larger than that of LDMOS devices, which is not conducive to the reduction of device loss characteristics. Small

Method used

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  • Lateral power device with mixed conduction mode and preparation method thereof
  • Lateral power device with mixed conduction mode and preparation method thereof
  • Lateral power device with mixed conduction mode and preparation method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0041] A lateral power device with a mixed conduction mode, the cellular structure and the cross-sectional view along the AA' line are as follows figure 2 and image 3 As shown, it includes a P-type substrate 1, a buried oxide layer 2, and an N-type drift region 3 arranged sequentially from bottom to top; one end of the N-type drift region 3 is provided with a P-type base region 4, and the other end is provided with an N-type A buffer zone 8; an N-type source region 5 and a P-type contact region 6 are arranged above the inside of the P-type base region 4, and a P-type collector region 9 is arranged above the inside of the N-type buffer region 8; the P-type contact region There is an emitter 10 above the region 6 and part of the N-type source region 5; the upper surface of the P-type collector region 9 has a collector 12; a gate dielectric layer 7 is also arranged above the P-type base region 4, and the gate There is a gate electrode 11 above the dielectric layer 7, the lengt...

Embodiment 2

[0050] Such as Figure 4 and Figure 5 As shown, the difference between this example and Example 1 is that there is an N-type layer 18 between the N-type strip 13 and the P-type strip 14 and the P-type RESURF layer 16, and the concentration of the N-type layer 18 is greater than The concentration of the N-type drift region 3 . Compared with Embodiment 1, this embodiment can further improve the current conduction capability of the lateral MOSFET.

Embodiment 3

[0052] Such as Figure 6 As shown, the difference between this example and Example 1 is that the P-type RESURF layer 16 is composed of a first sub-region 161 , a second sub-region 162 and a third sub-region 163 whose concentrations decrease from left to right. Compared with Embodiment 1, this embodiment can further improve the breakdown voltage of the device.

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Abstract

The invention provides a lateral power device with a mixed conduction mode and a preparation method thereof. The lateral power device comprises a P type substrate, a buried oxide layer, an N type drift region, a P type base region, an N type buffer region, an N type source region, and a P type contact region, a P type collector region, an emitter, a collector, a gate dielectric layer, and a gate electrode. An N type bar and a P type bar are formed on the surface of the N type drift region and are arranged on the surface of the device drift region at an interval in a direction perpendicular tothe channel length direction; and a P type RESURF layer is formed in the drift region below the N type bar and a P type bar. A dielectric trench structure is formed between the N type bar, the P typebar, and the P type RESURF layer and the N type buffer region. The concentrations of the N type bar and a P type bar are larger than that of the N type drift region; and the depth of the dielectric trench structure is not less than depths of the N type bar, the P type bar, and the P type collector region. According to the invention, mixed conduction of the surface SJ-LDMOS and LIGBT is realized; the low condition drop is obtained; the voltage-withstanding performance is improved; the switching speed is increased; the turn-off losses are reduced; the snapback effect is eliminated; and the device performance is improved.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a lateral power semiconductor device with a mixed conduction mode and a preparation method thereof. Background technique [0002] Lateral Insulated Gate Bipolar Transistor (LIGBT) is a lateral power device that combines the advantages of lateral power MOSFETs and bipolar transistors, and has the characteristics of high input impedance and reduced conduction voltage. , are widely used in various power integrated circuits. Compared with traditional devices based on bulk silicon technology, devices manufactured using SOI technology have many advantages such as fast speed, low power consumption, high integration density, strong anti-latch ability, low cost, and good radiation resistance. Therefore, LIGBT devices based on SOI materials also have the advantages of good insulation performance, low substrate leakage current, small parasitic capacitance an...

Claims

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Application Information

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IPC IPC(8): H01L29/739H01L29/06H01L27/12H01L21/84
CPCH01L21/84H01L27/1207H01L29/0615H01L29/0634H01L29/0649H01L29/7394
Inventor 张金平崔晓楠刘竞秀李泽宏任敏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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