The invention discloses a recovery circuit for improving the negative bias-temperature instability of a memory clock circuit. The recovery circuit comprises an enable signal terminal CEN, a clock signal terminal CLK, phase inverters I1, I2, I3, I4, I5, and I7, NOR gate I6, PMOS tube MP1, and NMOS tubes MN1 and MN2, and also comprises a recovery circuit with a NBTI effect. The recovery circuit with a NBTI effect comprises a PMOS tube MP2, a phase inverter I8, and a transmission gate I9. The source electrode of MP2 is connected to a high level terminal VDD, the drain electrode of MP2 is connected to the grid electrode of the MP1 tube, the grid electrode of MP2 is connected to the output terminal of the phase inverter I8 and NMOS grid terminal of transmission gate I9, the input terminal of the phase inverter I8 is connected to the enable signal terminal CEN and the PMOS grid terminal of transmission gate I9, one end of transmission gate I9 is connected to the grid electrode of MP1, and the other end is connected to a virtual bit line DBL. The provided recovery circuit can reduce the influence of NBTI effect on PMOS tube in the circuit so as to guarantee the highest work frequency of circuit and low energy consumption performance.