Manufacturing method of double diffusion field effect transistor

Abstract

The invention discloses a manufacturing method of a double diffusion field effect transistor, comprising the following steps: greatly increasing the saturation currents of the transistor by increasing the overlapped area of a transistor gate and drift region; changing the electric field distribution on the drift region using an extended grid potential so as to increase breakdown voltages; and synchronously, inhibiting the GIDL effect resulted from the overlapped area using the thick silicon dioxide under the gate at the overlapped area so as to reduce drain currents of transistor. In addition, the method can change the high-voltage breakdown position of the transistor from a transverse junction area to a longitudinal junction area, namely, the high-voltage breakdown position of the transistor is at the strongest junction area, thereby improving the voltage endurance of the double diffusion field effect transistor.

Description

technical field

[0001] The invention relates to semiconductor process technology, in particular to a method for manufacturing a double-diffusion field effect transistor. Background technique

[0002] For the existing semiconductor process technology, double diffused field effect transistor (Double Diffuse Drain MOS, DDDMOS for short) is a mainstream high-voltage device structure, which is widely used in driver chips and power devices.

[0003] Such as figure 1 As shown, in the prior art, the double-diffused transistor is generally manufactured according to the following method:

[0004] Firstly, performing ion implantation on the silicon substrate to form a well region, and then performing selective ion implantation in the well region to form a drift region;

[0005] Then, growing a gate silicon oxide layer on the well region;

[0006] The third step is to deposit a gate polysilicon layer on the gate silicon oxide layer;

[0007] The fourth step is to use known photolith...

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