P-type gate enhanced HEMT device and manufacturing method thereof

Abstract

The invention discloses a P-type gate enhanced HEMT device and a manufacturing method thereof. The method comprises steps that a heterojunction is manufactured, a gate, a source and a drain matched with the heterojunction are manufactured, a third semiconductor is formed on the heterojunction, the third semiconductor in the non-gate region is thinned, the third semiconductor in the non-gate regionis then converted into a fourth semiconductor, the third semiconductor in the gate region is retained, and the fourth semiconductor is a high-resistance semiconductor. The manufacturing method is advantaged in that no secondary extension is required, etching the gate region of the device is further not required, uniformity, repeatability and introduction of damage caused in the etching process are avoided, partial etching is performed on an active region besides the gate region of the device, and damage is reduced.

Description

technical field [0001] The invention relates to an enhanced HEMT device, in particular to a p-type gate enhanced HEMT device and a manufacturing method thereof, belonging to the technical field of semiconductor electronic switching devices. Background technique [0002] Group III nitride semiconductors are an important representative of the third-generation semiconductor materials. Compared with the first-generation and second-generation semiconductor materials, they have the advantages of large band gap, high breakdown electric field, high electron mobility and high saturation electron velocity. Therefore, group III nitride semiconductors have broad application prospects in the fields of industry, power systems, transportation, communications, and consumer electronics. Group III nitride semiconductor heterostructures, taking AlGaN / GaN heterojunction as an example, because the polarization effect can produce high concentration (>10 13 cm -2 ) and high electron mobility ...

AI Technical Summary

Problems solved by technology

Use p-GaN to increase the potential barrier at the AlGaN/GaN interface channel to above the Fermi level, so that the conductive channel under the gate is disconnected, the two-dimensional electron gas is exhausted, and the enhancement mode is realized; the realized device needs It is difficult to etch the p-GaN with a thickness of tens of nanometers outside the gate, and the process control is difficult and the repeatability is poor; the etching is easy to generate interface states, which will lead to aggravated device current collapse and affect device performance

figure 2 The enhancement-mode HEMT with selective area epitaxy p-GaN shown in , which uses p-GaN to enhance the AlGaN/GaN The potential barrier at the interface channel is above the Fermi level, so that the conductive channel under the gate is disconnected, the two-dimensional electron gas is exhausted, and the enhancement mode is realized; the enhancement mode device realized by it has a low threshold value, and it is difficult to achieve high Devices with a threshold voltage; process implementation is difficult, and epitaxial quality is not high; epitaxial p-GaN sidewalls are not steep, which affects subsequent processes

image 3 The hydrogen-passivated p-GaN enhancement-mode HEMT shown in , which depletes the two-dimensional electron gas below the gate by

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