114results about How to "Increase design margin" patented technology

A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does. Thereafter, the gate insulating film and the two layers of the nitrogen-containing inorganic insulating films are partially etched away in the opening of the organic resin film to expose the active layer of the TFT.

It is an object of the present invention to provide a semiconductor laser device with high-yielding in which a clack generated in an epitaxial growth layer is restrained and to the manufacturing method thereof, the semiconductor laser device includes a GaN substrate 1, an n-type GaN layer 2, an n-type AlGaN cladding layer 3, a n-type GaN guide layer 4, an InGaN multiple quantum well active layer 5, an undoped-GaN guide layer 6, a p-type AlGaN electron overflow suppression layer 7, a p-type GaN guide layer 8, a SiO₂ blocking layer 9, an Ni/ITO cladding layer electrode 10 as a transparent electrode, a Ti/Au pad electrode 11, and a Ti/Al/Ni/Au electrode 12. The SiO₂ blocking layer 9 is formed above the InGaN multiple quantum well active layer 5 so as to have an opening. The Ni/ITO cladding layer electrode 10 is formed inside the opening, and which is transparent for the light from the InGaN multiple quantum well active layer, and serves as a cladding layer.

A mesa-shaped piezoelectric resonator element including a resonator section having a thicker thickness than a peripheral section on the board surface of a piezoelectric substrate formed in a rectangular shape, wherein, when the length of the long side of the piezoelectric substrate is x and the board thickness of the resonator section is t, etching depth y of a level-difference section is set to fulfill a relationship in the following equation, based on the board thickness t. $\begin{array}{cc}y=-1.32\times \left(\frac{x}{t}\right)+43\pm 5& \left(\%\right)\end{array}$

To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer.

A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capacitors and one end side of the through electrode.

A capacitor built-in interposer of the present invention, includes a base resin layer, a capacitor first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively whereby the projection portion on one surface side of the base resin layer serves as a connection portion, a capacitor dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a capacitor second electrode for covering the dielectric layer, wherein a plurality of capacitors each constructed by the first electrode, the dielectric layer, and the second electrode are arranged and aligned in a lateral direction in a state that the capacitors are passed through the base resin layer.

An exemplary embodiment of the present invention is a semiconductor device having a regular layout region and an irregular layout region formed on one chip, including: a lower conductive layer; an interlayer insulating film formed on the lower conductive layer; an upper interconnect layer formed on the interlayer insulating film; and connection plugs disposed to electrically connect the lower conductive layer and the upper interconnect layer at a substantially shortest distance. In at least part of the regular layout region, the lower conductive layer and the upper interconnect layer are electrically connected to each other through at least two connection plugs and an intermediate connection layer for electrically connecting the at least two connection plugs, the at least two connection plugs being disposed at an immediately above position extending from immediately above the lower conductive layer and a shift position spaced apart from the immediately above position, respectively.

The present invention discloses a semiconductor package without outer pins and a stacked structure thereof. A first package is formed by arranging at least one chip on a lead frame and carrying out a potting procedure. The two ends of a plurality of contacts are exposed out of the first package, so at least one second package is connected with one of the ends of the contacts. Thus, a POP (package on package) novel multi-chip module structure is made by taking the lead frame of a QFN (quad flat non-leaded) package structure as the base frame.

The invention relates to a titanium-aluminum-tin alloy applied to a golf club head, which comprises the following materials in percentage by weight: 89 to 95 percent of titanium, 3.5 to 6.5 percent of aluminum and 1.5 to 3.5 percent of tin. The titanium-aluminum-tin alloy can be selectively added with trace elements such as niobium, vanadium, molybdenum, zirconium, chromium, iron, silicon, oxygen, nitrogen, and the like to form a high elongation material with the elongation of between 11 and 15 percent and the tensile strength of between 700 and 950 Mpa. The high elongation material can be applied to a body and a batter side of the golf club head; and by the design of an internal structure of the body and the design of a structure of balance weight and fins, products of the golf club head have good beating performance, shock controlling and golf controlling performances, adjustable angles and individuation.

The invention provides a clock circuit used for a high-speed high-precision SHA-less pipelined analog-to-digital converter. The clock circuit comprises first and second duty ratio stabilizing circuits and first to Nth output clock buffers. The first duty ratio stabilizing circuit generates a clock of which the duty ratio is adjustable and less than 50% and the clock is used for the first stage pipeline time sequence control. The second duty ratio stabilizing circuit generates a clock of which the duty ratio is 50% and the clock is used for the second stage to the Nth stage pipeline time sequence control. The first output clock buffer performs delay tuning on the clock outputted by the first duty ratio stabilizing circuit so as to realize time sequence alignment of the first stage pipeline and the subsequent stage pipeline. The second to the Nth output clock buffers drive the clock outputted by the second duty ratio stabilizing circuit. The two duty ratio stabilizing circuits are connected in series. Time sequence distribution of the first stage pipeline is enabled to be optimized by the clock of which the duty ratio is less than 50% so as to reduce the design difficulty of an operational amplifier, and the second to the Nth stage time sequences are enabled to be optimized by the clock of which the duty ratio is 50% so as to increase the reuse degree of the unit circuit.

The invention discloses a welding method and clamp of a Venturi tube with a bend. The welding method comprises the steps of: respectively clamping and positioning an inlet section and an outlet section of a Venturi tube with a transition section for welding; sequentially spot-welding all spots on a butt seam corresponding to arcs of 0 degree->180 degrees->270 degrees->450 degrees->495 degrees->675 degrees; carrying out sealing welding along the clockwise rotation from the starting point of the butt seam, and after welding the butt seam for one circle, starting arc extinguishing in a place exceeding the starting point by 15 degrees, so as to complete the sealing welding; and selecting a point, between which and the starting point the arc angle is 180 degrees, as another starting point to perform welding, and after welding for one circle, starting the arc extinguishing in a place exceeding the starting point by 15 degrees, so as to complete the welding. The clamp comprises a center shaft with a bend, wherein an inlet inner sleeve and an outlet inner sleeve are sleeved on the center shaft, the outer edge surfaces of the inner sleeves are clung to the inner wall of the Venturi tube, and protection sleeves are respectively arranged on two ends of the inner sleeves, and clamping flanges are respectively arranged on opening ends of an inlet section and an outlet section and are fixed through nuts. According to the welding method and the clamp disclosed by the invention, the Venturi tube with a wall thickness of 1-3mm and the bend of 3-8 degrees can be welded.

The present invention discloses a multi-chip semiconductor package structure without outer leads and a lead frame thereof. At least one group of first contacts and at least one group of second contacts, having different heights, are formed on a lead frame and arranged around a chip placement zone preset. The chip placement zone is used for placing a first chip and stacking a second chip. The first contacts are electrically connected to the active surface of the first chip of the most similar height by a plurality of first electrical connecting elements. The second contacts are electrically connected to the active surface of the second chip of the most similar height by a plurality of second electrical connecting elements. Thus, a novel multi-chip module structure of multiple stacked chips is made by taking the lead frame of a QFN (quad flat non-leaded) package structure as the base frame.

A motor and its bearing supporting structure are disclosed. The bearing supporting structure supporting a shaft includes a bushing, a bearing and at least one first limiting assembly. The bushing has an opening and an accommodating space. The bearing supports at least a portion of the shaft and is disposed in the accommodating space. The first limiting assembly is disposed at a connection of the bearing and the bushing.