Packaging structure of multi-chip semiconductor

Abstract

The invention discloses a packaging structure of a multi-chip semiconductor, at least a first chip is placed on a wire guide frame, and two ends of a plurality of contact points after the first adhesive sealing procedure, thereby utilizing one end of each contact point for connecting at least one second chip; and then carrying out the second adhesive sealing procedure, thereby realizing an completely new multi-chip module structure which is constructed by taking the wire guide frame with a quad flat non-leaded (QFN) packaging structure as a foundation frame and similar to a package in package (PIP) stacking body.

Description

【Technical field】 [0001] The present invention relates to a multi-chip semiconductor package structure, in particular to a quad flat no-lead (QFN) package structure with multiple chips. 【Background technique】 [0002] Nowadays, in order to meet various high-density packaging requirements, the semiconductor packaging industry has gradually developed various types of packaging structures, among which various system in package (SIP) design concepts are often used to build high-density packaging structures. Generally speaking, system packaging can be divided into multi chip module (MCM), package on package (POP) and package in package (PIP). The multi-chip module (MCM) refers to arranging several chips on the same substrate. After setting the chips, all the chips are embedded with the same encapsulation gel, and can be subdivided into stacked chips ( stacked die) package or parallel chip (side-by-side) package. Furthermore, the stacked-package-on-package (POP) structure refers...

AI Technical Summary

Problems solved by technology

[0005] Although Figure 1B The single-chip quad flat no-lead package structure shown is beneficial to achieve high pin density packaging because it has multiple groups of contacts 112, but when the number of groups (that is, the number of rows) of the contacts 112 is greater than 4 groups or more When the wire bonding procedure of the wire 13 becomes complicated and difficult, that is, the wire 13 is too long, the bending points required for a single wire 13 increase, and the wire bonding between the wires 13 Technical problems such as complex staggered arrangement, which increase consumption cost and design difficulty

At the same time, during the molding process of the encapsulant 14, the flowing encapsulation material will easily push the overly long wires 13, causing the adjacent wires 13 to contact each other and cause a short circuit, thereby increasing the problem of defective products.

[0006] Therefore, it is necessary to provide a multi-chip semiconductor packaging structure to solve the existing high-density packaging problems when the existing quad flat no-lead (QFN) packaging technology is applied to the field of multi-chip modules

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