Multi-chip semiconductor package structure without outer leads and lead frame thereof

Abstract

The present invention discloses a multi-chip semiconductor package structure without outer leads and a lead frame thereof. At least one group of first contacts and at least one group of second contacts, having different heights, are formed on a lead frame and arranged around a chip placement zone preset. The chip placement zone is used for placing a first chip and stacking a second chip. The first contacts are electrically connected to the active surface of the first chip of the most similar height by a plurality of first electrical connecting elements. The second contacts are electrically connected to the active surface of the second chip of the most similar height by a plurality of second electrical connecting elements. Thus, a novel multi-chip module structure of multiple stacked chips is made by taking the lead frame of a QFN (quad flat non-leaded) package structure as the base frame.

Description

【Technical field】 [0001] The present invention relates to a multi-chip semiconductor packaging structure without external leads and a lead frame, in particular to a quad flat no-lead (QFN) package structure and lead frame for carrying multiple chips. 【Background technique】 [0002] Nowadays, in order to meet various high-density packaging requirements, the semiconductor packaging industry has gradually developed various types of packaging structures, among which various system in package (SIP) design concepts are often used to build high-density packaging structures. Generally speaking, system packaging can be divided into multi chip module (MCM), package on package (POP) and package in package (PIP). The multi-chip module (MCM) refers to arranging several chips on the same substrate. After setting the chips, all the chips are embedded with the same encapsulation gel, and can be subdivided into stacked chips ( stacked die) package or parallel chip (side-by-side) package. F...

AI Technical Summary

Problems solved by technology

[0005] Although Figure 1B The single-chip quadflat no-lead package structure shown is beneficial to achieve high pin density packaging because it has multiple groups of contacts 112, but when the number of groups (that is, the number of rows) of the contacts 112 is greater than 4 groups or more Oftentimes, the procedure of wire bonding (wire bonding) of the wire 13 will become complicated and difficult, that is, the wire 13 is too long, the number of bending points required for a single wire 13 increases, and the gap between the wire 13 There are technical problems such as complex staggered arrangement among them, which increases consumption cost and design difficulty

At the same time, during the molding process of the encapsulant 14, the flowing encapsulation material will easily push the overly long wires 13, causing the adjacent wires 13 to contact each other and cause a short circuit, thereby increasing the problem of defective products.

[0006] Therefore, it is necessary to provide a multi-chip semiconductor packaging structure without external leads to solve the high-density packaging problems existing when the existing quad flat no-leads (QFN) packaging technology is applied to the field of multi-chip modules

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