A sensitive amplifier circuit with ultra-low offset

Abstract

The invention discloses a sensitive amplifier circuit with ultra-low offset. According to the sensitive amplifier structure, the offset voltage can be greatly reduced, amplification of the bit line voltage difference and storage compensation of the threshold voltage difference are achieved through the capacitor storage voltage and the characteristic that the voltage is not suddenly changed, and the effect of greatly reducing the offset voltage is achieved. Meanwhile, along with great reduction of offset voltage, the data reading speed of the static random access memory can be effectively increased, the energy consumption during unit reading is reduced, and the margin of the reading voltage of the static random access memory is effectively improved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a sensitive amplifier circuit with ultra-low offset. Background technique [0002] Since the appearance of the first computer, memory, as the core component of the computer, has also been continuously developed. Static Random Access Memory (SRAM for short) is one of the most widely used memories in computers because of its high speed and low power consumption. SRAM mainly implements two operations of reading and writing. Since the parasitic capacitance of the bit line is greater than the internal parasitic capacitance of the unit, the reading operation time of data is longer than the writing operation time. In order to improve the operating frequency of SRAM, a sense amplifier (Sense Amplifier, abbreviated as SA) was proposed Used to speed up the reading of data. Under ideal conditions, the input terminal of the sense amplifier only needs to input two extremely small vo...

AI Technical Summary

Problems solved by technology

It has a good effect in improving the offset voltage, but the timing signal is more complicated, and there is a certain consumption of the timing circuit area.

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