3results about How to "Reduce saturation current" patented technology

The invention discloses a power semiconductor device and a preparation method thereof. The power semiconductor device comprises a substrate, and the substrate comprises a substrate and an epitaxial layer located on the substrate; a plurality of first cells and second cells, wherein the first cells and the second cells are arranged in parallel in the first direction; the second cell comprises communication grooves penetrating from the surface of the epitaxial layer to the interior of the epitaxial layer, the communication grooves comprise second grooves and third grooves, and the third grooves are located between the adjacent second grooves and are communicated with the adjacent second grooves; the well regions are located in the epitaxial layer, the well regions extend into the epitaxial layer from the surface of the epitaxial layer, and the well regions are located on the two sides of the communicating groove; the second cell comprises a first region, a well region between adjacent second grooves of the first region in the second cell further comprises a first part well region and a second part well region, the first part well region is close to the third groove, the second part well region is far away from the third groove, the first source region is located on the surface of the second part well region, and no source region exists on the surface of the first part well region.

A kind of high short-circuit capability IGBT device, including trench on N type substrate, the P type trap region is below the trench outside, the conductive channel of the IGBT device is located in P trap type region near the side wall of trench, when the device gate applies voltage and makes the device open, the width of each channel in vertical direction remains consistent, the error value of channel width does not exceed the maximum error value set.The high short-circuit capability IGBT device of the utility model, inhibits the appearance of device short channel effect, reduces the saturation current of device, improves short-circuit capability, simultaneously, because P type trap region average concentration is higher than traditional structure, therefore, bulk region resistance reduces, and the anti-latch-up capability of device is improved.

The invention belongs to the technical field of power devices, and provides a device preparation method based on a self-alignment patterning process and a chip, the growth morphology of a self-alignment material is controlled through different selection ratios, the injection range of P-type doped ions is adjusted through an etching mode, a P-type shielding region is formed at the bottom of a groove of an N-type drift region, and the P-type shielding region is formed at the bottom of the groove of the N-type drift region. The growth morphology of a hard mask is controlled through the selection ratio of different self-alignment materials, a corner dielectric layer is arranged in a groove corner region of an N-type drift region, and a plurality of P-type floating ring regions of which the widths are gradually reduced from a current expansion layer to a drain electrode layer are arranged in a central region of the N-type drift region. The widths of the plurality of P-type floating ring regions are gradually reduced from the P-type shielding region to the drain electrode layer, so that the distribution range of a high electric field in the drift region can be expanded, the area of a space charge region is increased, the saturation current of the device is effectively reduced, the endurance capability of the device under a short-circuit test is improved, and the reliability of the device is improved.