59results about How to "Reduce saturation current" patented technology

The invention relates to an insulated gate bipolar transistor (IGBT) with low-conductivity saturation voltage drop and a manufacturing method for the IGBT. A second conductive type layer is arranged in an active region and partitioned into a plurality of second conductive type layer first regions and a second conductive type layer second regions by conductive polysilicon and insulated gate medium layers; an insulation medium layer is covered on the first main surface of a semiconductor substrate; first conductive type injection regions are symmetrically arranged in the second conductive type layer first regions and contacted with the corresponding insulated gate medium layers; emitter contact holes are formed above the second conductive type layer second regions, pass through the insulation medium layer and extend to the first main surface; emitter metal layers are filled in the emitter contact holes and covered on the insulation medium layer; and the emitter metal layers are in ohm contact with the second conductive type layer first regions. The IGBT has relatively low saturation voltage drop Vcesat and relatively high impact resistance.

The invention discloses a flat coil inductor, a flat coil and a manufacture method of the flat coil. The flat coil inductor comprises a magnetic core, a magnetic cover covering the magnetic core and the flat coil coiled on the magnetic core, wherein the magnetic core is provided with, at least, a first groove and a second groove. The flat coil comprises, at least, the top end base portion and two side edge flattening portions, wherein the base portion is larger than the side edge flattening portions in thickness, the side edge flattening portions are larger than the base portion in width, the base portion is embedded into the first groove, and the side edge flattening portions are embedded into the second groove. The side edge flattening portions are formed by locally flattening the flat coil of the inductor, so that different thicknesses are obtained, the side edge flattening portions are larger than the base portion in width but are smaller than the base portion in thickness, and a magnetic core accommodating space defined by the flat coil is increased. The magnetic core can be matched and assembled with a large corresponding magnetic core, so that the direct-current resistance of the inductor in a limited size range is decreased, the saturation current is increased, and the inductor can obtain the best electrical characteristics.

The invention belongs to the field of power semiconductors, and particularly provides a SiC power device. The SiC power device comprises a SiC MOSFET and a SiC IGBT. For the SiC MOSFET device integrated with a PN junction body diode, the reverse recovery charge and related loss of the body diode can be greatly reduced, the reverse recovery peak current is reduced, and the EMI noise is reduced; forthe SiC MOSFET device integrated with an N-type Schottky diode or an integrated heterojunction diode, the voltage drop during reverse conduction of the MOSFET can be reduced, and the minority carrierinjection effect is eliminated, so that the conduction loss and reverse recovery loss of the diode are reduced; for the reverse conduction type SiC IGBT device integrated with the PN junction body diode, the reverse recovery charge and related loss of the body diode can be greatly reduced, the reverse recovery peak current is reduced, and the EMI noise is reduced; and moreover, for the reverse conduction type SiC IGBT device integrated with the N-type Schottky diode or the heterojunction diode, the voltage drop during reverse conduction of the reverse conduction IGBT can be reduced, the minority carrier injection effect is eliminated, and the conduction loss and reverse recovery loss of the diode are reduced.

The invention discloses a double-staggered flyback photovoltaic grid-connected micro inverter and a control method thereof. The double-staggered flyback photovoltaic grid-connected micro inverter comprises a direct-current-side capacitor, a double-flyback converter, a converter bridge and an output filter, wherein two high-frequency transformers of the double-staggered flyback converter respectively have a double-secondary winding structure, so a system can work in a staggered flyback mode at any time, and requirements of the system on the saturation current of the high-frequency transformers, magnetic cores, input output capacitance and the rated current of a power metal oxide semiconductor field effect transistor (MOSFET) are reduced; the converter bridge consists of two thyristors; and by using an active conversion method, the quality of grid-connected current waveform is ensured on the premise that the reliability of the system is ensured. The double-staggered flyback photovoltaic grid-connected micro inverter can efficiently convert and transmit energy without pollution, and has the characteristics of compact structure, low cost, reliability and practicability.

The invention discloses a double-groove type SiC MOSFET cellular structure and device and a manufacturing method thereof, the double-groove type SiC MOSFET cellular structure comprises an N + + type SiC substrate, an N-type SiC drift layer, a P type base region and an N + type source region, the N-type SiC drift layer is located above the N + + type SiC substrate and is provided with a source electrode groove and a grid electrode groove, and the bottom of the source electrode groove is provided with an N type hole blocking layer and a source electrode P + type shielding layer; an N-type current conducting layer and a grid P + type shielding layer are arranged at the bottom of the grid groove, and a grid dielectric layer and a grid electrode are arranged in the grid groove; the P-type base region and the N + type source region are located on the N-type SiC drift layer between the source trench and the gate trench and are arranged from bottom to top. Shielding of the drain voltage is further enhanced, the electric field peak value and the gate-drain capacitance of the gate dielectric layer are reduced, the reliability of the gate dielectric layer and the working frequency of the device are improved, the on-resistance of the device can be reduced, and the short-circuit capability of the device can be enhanced.

This invention relates to the power semiconductor field, providing a trench gate IGBT device with carrier storage which is used for solving the problems of high saturation voltage, small short circuitsafe working area and limited concentration of the existing trench gate IGBT device with carrier storage layer, and put forward a novel trench gate IGBT device with carrier storage layer. The trenchgate IGBT device with carrier storage layer directly integrates a plurality of series diodes on the surface of silicon wafers to clamp the potential of the electric field shielding layer in the P region, thereby breaking the concentration limit of CSL on the basis of trench gate IGBT process, greatly improving the injection efficiency of IGBT emitter and greatly improving the trade-off relation between forward voltage drop and turn-off loss of IGBT. Meanwhile, due to the clamping effect of the diode, the drain near the IGBT nMOS channel is clamped at a lower voltage under high voltage and large current, thereby greatly reducing the saturation current of the novel IGBT and improving the short circuit safe working area of IGBT.

The invention relates to the field of power semiconductors, provides an IGBT device with a carrier storage layer using diode clamping, and solves the problems that the saturation voltage of an existing groove gate IGBT with the carrier storage layer (CSL) is high, a short circuit safe working area is smaller, and the CSL concentration is limited. The IGBT device with the carrier storage layer using diode clamping has the advantages that the IGBT directly integrates one or more series diodes on the surface of a silicon wafer through a groove gate IGBT process for clamping electric potential ofan electric field shielding layer of a P region, on the basis of the groove gate IGBT process, the limitation of the CSL concentration is broken through, the injection efficiency of an IGBT emitting electrode is greatly improved, thereby greatly improving the tradeoff relationship between conduction voltage drop and turn-off loss of the IGBT; due to the clamping action of a diode, a drain electrode near an nMOS channel of the IGBT is clamped at a lower voltage under the high voltage and large current, so that saturation current of the novel IGBT is reduced to a great extent, thereby enlargingthe short circuit safe working area of the IGBT.

The invention provides a memory structure and a forming method thereof. The memory structure comprises a first transmission transistor and a second transmission transistor, wherein the first transmission transistor comprises a first transmission drain region and a first transmission source region; the first transmission source region and the first transmission drain region are provided with firstdoped ions; the concentration of the first doped ions in the first transmission drain region is different from that in the first transmission source region; the second transmission transistor comprises a second transmission drain region and a second transmission source region; the second transmission source region and the second transmission drain region are provided with second doped ions; and the concentration of the second doped ions in the second transmission drain region is different from that in the second transmission source region. The writing ability of a memory can be improved whilethe noise reading capacity of the memory is improved.

The invention relates to a junction field-effect transistor and a manufacturing method thereof. The junction field-effect transistor obtained by the manufacturing method includes an N-type substrate,an N-type epitaxial layer, a buried P-type gate region formed in the N-type epitaxial layer, an oxide layer, a gate trench penetrating through the oxide layer and extending to the P-type gate region,a P-type diffusion region formed on the inner wall of the gate trench and connected to the P-type gate region, polysilicon formed in the gate trench, an N-type region formed on the surface of the N-type epitaxial layer, an opening penetrating through the oxide layer and corresponding to the N-type region, gate metal formed on the oxide layer and the gate trench and connected to the polysilicon, source metal, and drain metal. The P-type gate region includes a plurality of first parallel bar portions and a plurality of second bar portions perpendicularly intersecting with the first bar portions,the outermost second bar portion being in contact with the gate trench and the P-type diffusion region, and the first bar portion at one side of the outermost second bar portion and the second bar portion being located below the N-type region.

The invention belongs to the technical field of power semiconductors, and particularly relates to an SOI LIGBT device integrated with a Zener diode. Compared with a traditional LIGBT, the Zener diodeis introduced into a P well region at an emitter end of a new device, the P-type region of the Zener diode is electrically connected with the emitter of the device, and the N-type region of the Zenerdiode is electrically connected with the P well region through floating ohmic metal. When the voltage of a collector electrode is continuously increased, the Zener diode is reversely broken down and conducted, so that the potential of the P well region is clamped, the gate capacitance of the device can be reduced, the saturation current can be reduced to improve the short-circuit capability of thedevice when the device is conducted, and a hole extraction path can be provided in the turn-off process to reduce the turn-off time and the turn-off loss. Compared with a traditional LIGBT structure,the novel LIGBT structure provided by the invention has the advantages that a better compromise relationship between conduction voltage drop and turn-off loss is obtained, and the short-circuit resistance of the device is improved.

The invention provides a segmented injection self-clamping IGBT and a manufacturing method thereof. A trench structure equipotential with an emitter is introduced to the right side of a cell, the P-type doped buried layers are introduced below an N-type charge storage layer, and the high-concentration P-type buried layers are distributed at intervals by changing an opening of a mask plate, so that the adverse effect of the high-concentration P-type buried layers on the threshold voltage when a device is conducted is improved, and the on-resistance is reduced. When the device is saturated, a self-biased PMOS structure is opened, and the electric potential of a CS layer is clamped at a lower value, so that the saturation current of the IGBT is reduced. The high-concentration P-type buried layers distributed at intervals can ensure that the PMOS structure is normally started under high collector voltage so as to clamp the potential of the CS layer, the saturation current is reduced, and the short-circuit capability of the device is improved. On the basis of a traditional trench IGBT process method, the P+ buried layers distributed in a segmented mode in a z direction can be achieved only by adding one mask, the process complexity is not increased, and implementation is easy.

The invention belongs to the technical field of cable measuring, and particularly relates to a cable temperature and load current measuring wireless device based on induction power taking, which comprises a shell and a power taking and current measuring ring, and is characterized in that the shell comprises an upper shell, a middle shell and a lower shell which are detachable; a main control board and a wireless communication module are fixed in the middle shell; the power taking and current measuring ring is fixedly arranged on the shell and penetrates through a measured cable; the power taking and current measuring ring comprises a detachable annular soft magnetic alloy belt and a Rogowski coil; and and a temperature probe is fixed below the lower shell. The soft magnetic alloy belt is adopted to take power, and the soft magnetic alloy belt is soft and can be easily installed on measured objects in different shapes. The Rogowski coil is used for current measuring, large current does not generate heat, the measuring range is wide, the size is small, the weight is light, and the opening is easy to install. The device is easy to install, Rogowski coils and soft magnetic alloy belts of different sizes can be replaced for measured objects of different sizes, and adaptability and universality are high.

Dynamic memory cell, a conductive surface-tape contact (20) is the conductive connection between a channel-capacitor (1) and a proliferation district (3) of an planar selecting transistor (2) formed by the channel-capacitor (1) and a DRAM memory cell (101) of the planar selecting transistor (2), and the contact (20) is located above the substrate surface and at least covers part of the proliferation district (3). Memory nodes (15) of the channel Capacitor (1) is closed by at least one oxide ring sheath (21), which can insulate the memory nodes (15) and the proliferation district (3, 4) at the substrate side. An oxide cover(23) is provided on the oxide ring sheath (21). An opening (24) filled up with a conductive material, located in the oxide cover(23), is connected to the conductive surface-tape contact, and the scope of the opening ( 24) is extended vertically from the surface of the oxide cover(23) to the memory node (15). A favorable configuration has a memory cellular field formed by a plurality of MINT memory cells with a area of 8 F # + [2], wherein the initiative area is formed by a plurality of strip memory cells on the beam.