Memory structure and method of forming the same

A technology of memory and storage area, which is applied in the direction of semiconductor devices, electric solid state devices, electrical components, etc., and can solve the problems of small reading noise capacity and poor reading and writing ability

Active Publication Date: 2020-12-22
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, the memory formed by the prior art still has the disadvantages of low read noise capacity and poor read and write capabilities

Method used

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  • Memory structure and method of forming the same
  • Memory structure and method of forming the same
  • Memory structure and method of forming the same

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Experimental program
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Embodiment Construction

[0037]The memory structure of the prior art has many problems, for example, the static noise capacity of the static memory is small, and the anti-interference ability is poor.

[0038]Now combine the memory of the prior art to analyze the reasons for the low static noise capacity of the memory and poor anti-interference ability:

[0039]figure 1 It is a schematic diagram of a static memory structure.

[0040]Please refer tofigure 1 The static memory includes: a first pull-up transistor PU1, a first pull-down transistor PD1, a first transfer transistor PG1, a second pull-up transistor PU2, a second pull-down transistor PD2, and a second transfer transistor PG2. The source of the first pull-up transistor PU1 is connected to the drain of the first pull-down transistor PD1 to form a first storage node A. The source of the second pull-up transistor PU2 is connected to the drain of the second pull-down transistor PD2. The drains are connected to form a second storage node B. The gate of the first ...

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Abstract

The present invention provides a memory structure and its formation method. Among them, the memory structure includes: the first transmission transistor, which includes the first transmission leakage area and the first transmission source area, the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area and the first transmission source area.There is a first doped ion in the transmission leakage area, which is different from the first doped ion concentration in the first transmission leakage area.The second transmission transistor includes the second transmission leakage area and the second transmission source area. The second transmission source area and the second transmission leakage area have a second doped ionThe concentration of the doped ion is different from the second doped ion concentration in the second transmission source area.The memory can improve the memory writing ability while increasing the read noise capacity of the memory.

Description

Technical field[0001]The present invention relates to the technical field of semiconductor manufacturing, in particular to a memory structure and a method of forming the same.Background technique[0002]With the development of information technology, the amount of stored information has increased dramatically. The increase in the amount of stored information promotes the rapid development of the memory, and at the same time puts forward higher requirements for the stability of the memory.[0003]The basic static memory (Static Random Access Memory, SRAM) relies on six transistors, which form two cross-coupled inverters. Each inverter includes: a pull-up transistor, a pull-down transistor and an access transistor.[0004]In order to obtain sufficient anti-interference ability and read stability, most of the transistors used to form a memory are Fin Field-Effect Transistor (FinFET). In FinFET transistors, the gate is a 3D structure covering the three surfaces of the fin, which can greatly i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11
CPCH10B10/12
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP
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