Write buffer detector, addressing method of written data and parallel channel write method

Abstract

The invention provides a solid state disk (SSD) controller based on a write buffer detector, an addressing method of written data and an optional parallel channel write method, which achieve accurate judgment on address characteristics of data, respectivelycache continuous address data and random address data, write different write strategies according to different data types, and improve write speed of random data. The write buffer detector comprises an address subtractor, a continuous data buffer and a random data buffer, wherein the address subtractor is used for conducting subtraction on current page addresses and previous page addresses and comprises a previous page address register and a current page address register, the previous page address register is used for storing data and addresses at the previous page, and the current page address register is used for storing data and addresses at the current page; the size of the continuous data buffer is set to be a parameter Sequential-Buffer-Size, the continuous data buffer is used for caching data which is probably judged to be continuous access data, and data in the continuous data buffer is judged to be continuous data if the length of data in the continuous data buffer reaches the set parameter; and the random data buffer is used for caching random access data.

Description

technical field [0001] The invention relates to the field of data storage, in particular to a solid-state hard disk controller with a write buffer detector (Buffer Detector), an addressing method for writing data, and a parallel channel writing method. Background technique [0002] The rapid development of flash memory technology will make flash memory (flash memory) become the dominant device of secondary memory. Compared with traditional hard disks, flash memory has the following main advantages: low power consumption, shock resistance, high storage density, non-volatility, and faster access speed. [0003] At present, flash memory technology can be divided into two categories: NOR flash memory and NAND flash memory. The NOR type has independent data lines and address lines, can be read randomly, can be single-byte programmed, but cannot be single-byte erased. But the erasing time is long, the unit cost is high, and the code can be read and executed directly from the fla...

AI Technical Summary

Problems solved by technology

[0004] Compared with traditional hard disks, flash storage technology has specific inherent defects: cannot directly rewrite data in flash memory (write before erase), longer erasing time (about 1.5ms), limited erasing times (single-layer storage (SLC) can usually be erased 100,000 times, and multi-layer storage (MLC) can usually be erased 10,000 times)

[0011] Based on the above analysis, there are at least the following problems in the prior art: 1. The LAST algorithm cannot accurately determine the continuity and randomness of data access; 2. Since the prior art cannot accurately determine the continuity and randomness of data access, it cannot As a result of the judgment, different writing methods are used; 3. The writing performance under random access cannot meet the requirements

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