Write buffer detector, addressing method of written data and parallel channel write method

A detector and data buffer technology, applied in the direction of input/output to record carrier, memory address/allocation/relocation, etc., can solve the problems of long erasing time, limited erasing times, and inability to directly rewrite data, etc. The effect of preventing misjudgment or omission, improving performance and reducing overhead

Inactive Publication Date: 2012-06-27
SHANGHAI JIAO TONG UNIV
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Problems solved by technology

[0004] Compared with traditional hard disks, flash storage technology has specific inherent defects: cannot directly rewrite data in flash memory (write before erase), longer erasing time (about 1.5ms), limited erasing times (single-layer storage (SLC) can usually be erased 100,000 times, and multi-layer storage (MLC) can usually be erased 10,000 times)
[0011] Based on the above analysis, there

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  • Write buffer detector, addressing method of written data and parallel channel write method
  • Write buffer detector, addressing method of written data and parallel channel write method
  • Write buffer detector, addressing method of written data and parallel channel write method

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[0040] The invention is a design method of a flash memory conversion layer based on a write buffer detector, which is mainly used for realizing accurate judgment of address characteristics of write data, and respectively buffering continuous address data and random address data. Different write strategies are used for different data types. Because the writing of random data is the current bottleneck in the performance of flash memory, the present invention proposes an optional parallel multi-channel technology to effectively improve the writing performance of random data.

[0041] The technical solutions of the present invention will be described in detail below in conjunction with specific embodiments. In order to better refer to the technical solution of the present invention, please combine figure 1 A schematic structural diagram of a system including the write buffer detector of the present invention is shown. The upper file system 100 passes through the controller 200 ,...

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Abstract

The invention provides a solid state disk (SSD) controller based on a write buffer detector, an addressing method of written data and an optional parallel channel write method, which achieve accurate judgment on address characteristics of data, respectivelycache continuous address data and random address data, write different write strategies according to different data types, and improve write speed of random data. The write buffer detector comprises an address subtractor, a continuous data buffer and a random data buffer, wherein the address subtractor is used for conducting subtraction on current page addresses and previous page addresses and comprises a previous page address register and a current page address register, the previous page address register is used for storing data and addresses at the previous page, and the current page address register is used for storing data and addresses at the current page; the size of the continuous data buffer is set to be a parameter Sequential-Buffer-Size, the continuous data buffer is used for caching data which is probably judged to be continuous access data, and data in the continuous data buffer is judged to be continuous data if the length of data in the continuous data buffer reaches the set parameter; and the random data buffer is used for caching random access data.

Description

technical field [0001] The invention relates to the field of data storage, in particular to a solid-state hard disk controller with a write buffer detector (Buffer Detector), an addressing method for writing data, and a parallel channel writing method. Background technique [0002] The rapid development of flash memory technology will make flash memory (flash memory) become the dominant device of secondary memory. Compared with traditional hard disks, flash memory has the following main advantages: low power consumption, shock resistance, high storage density, non-volatility, and faster access speed. [0003] At present, flash memory technology can be divided into two categories: NOR flash memory and NAND flash memory. The NOR type has independent data lines and address lines, can be read randomly, can be single-byte programmed, but cannot be single-byte erased. But the erasing time is long, the unit cost is high, and the code can be read and executed directly from the fla...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F3/06G06F12/02
Inventor 周鸿蒋江
Owner SHANGHAI JIAO TONG UNIV
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