7results about How to "Improve short circuit performance" patented technology

The invention discloses a manufacturing method of an MOSFET structure and the MOSFET structure, and the method comprises the steps: carrying out the ion implantation on a wafer to form a p-type shielding region, and etching grooves in the wafer, the wafer comprises a first current transmission layer and a second current transmission layer, and the grooves are distributed at the two sides of the second current transmission layer; forming doped regions below the grooves, wherein the doped regions are located at the two sides of the second current transmission layer; growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, and etching and depositing polycrystalline silicon on the eighth barrier layer through photoresist to form two gate regions; and forming an oxidation dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxidation dielectric layer and the second current transmission layer, depositing a drain region at the bottom of the wafer, and performing ohmic contact and Schottky contact. The gate oxide and the Schottky contact region are protected through the p-type shielding region and the doped region, the conductive current path width is controlled, the saturation current is reduced, and the short-circuit capability and the reliability are improved.

The invention relates to an N-pole module assembly of a circuit breaker and the circuit breaker. The N-pole module assembly of the circuit breaker comprises a main body function module and a current detection module, and further comprises a first N-pole conductive plate fixedly integrated on the main body function module and a second N-pole conductive plate fixedly integrated on the current detection module, and the main body function module and the current detection module are respectively two independent modular structures. And the first N-pole current-conducting plate and the second N-pole current-conducting plate are fixedly and electrically connected to form an N-pole electric loop. According to the invention, the complicated bending and wiring process of the soft wire in the N-pole module assembly in the prior art is avoided, the assembly is convenient, and the automatic assembly can be realized. Moreover, through the special arrangement of the relative positions of the N-pole electric loop and the L-pole electric loop, the Lorentz force generated by the magnetic field generated by the current on the N-pole electric loop on the electric arc in the circuit breaker unit can assist the electric arc to be further pushed and lengthened, and the effect of enhancing the magnetic quenching function can be achieved.

The present invention discloses a method for manufacturing a MOSFET structure and a MOSFET structure, the method comprising: performing ion implantation on a wafer to form a p-type shielding region, and etching a groove on the wafer, the wafer comprising a first current transmission layer and a second current transmission layer, the grooves being distributed on both sides of the second current transmission layer; forming a doped region on both sides of the second current transmission layer; growing a gate oxide layer and an eighth barrier layer on the doped region and the wafer, etching the eighth barrier layer through photoresist and depositing polysilicon to form two gate regions; forming an oxidized dielectric layer to wrap the gate region, depositing a source region and a Schottky contact region on the doped region, the oxidized dielectric layer and the second current transmission layer, and depositing a drain region at the bottom of the wafer to perform ohmic contact and Schottky contact. The present invention protects the gate oxide and the Schottky contact region through the p-type shielding region and the doped region, controls the width of the conductive current path, reduces the saturation current, and improves the short-circuit capability and reliability.

The invention relates to a preparation method of an RC-IGBT device and the RC-IGBT device, and belongs to the technical field of semiconductors. Comprising the following steps: forming a gate electrode, an emitter and a diode anode of the RC-IGBT device on the surface of one side of an epitaxial layer; injecting protons into the surface of one side, far away from the gate electrode, the emitter and the diode anode, of the epitaxial layer to form a composite epitaxial layer; forming a first drift region on the surface of one side, far away from the gate electrode, the emitter and the diode anode, of the composite epitaxial layer; forming a second drift region on the surface of one side, away from the composite epitaxial layer, of the first drift region; and forming a collector electrode and a diode cathode of the RC-IGBT device on the surface of one side, far away from the first drift region, of the second drift region. The diode is constructed in the IGBT device in a proton injection mode, the reverse recovery performance of the diode can be improved without controlling the service life of a carrier, and the performance of the IGBT and the reverse recovery performance of the diode are both considered.

A kind of high short-circuit capability IGBT device, including trench on N type substrate, the P type trap region is below the trench outside, the conductive channel of the IGBT device is located in P trap type region near the side wall of trench, when the device gate applies voltage and makes the device open, the width of each channel in vertical direction remains consistent, the error value of channel width does not exceed the maximum error value set.The high short-circuit capability IGBT device of the utility model, inhibits the appearance of device short channel effect, reduces the saturation current of device, improves short-circuit capability, simultaneously, because P type trap region average concentration is higher than traditional structure, therefore, bulk region resistance reduces, and the anti-latch-up capability of device is improved.

The invention relates to a silicon carbide plane gate MOSFET device and a manufacturing method thereof in the technical field of semiconductors. Comprising a substrate, a drain electrode formed on one end face of the substrate, an epitaxial layer formed on the other end face of the substrate, a current diffusion layer formed above the epitaxial layer, an epitaxial well region formed above the epitaxial layer, a first source contact region formed in the epitaxial well region and a second source contact region formed in the epitaxial well region, a source electrode is further arranged on the second source contact region, the source electrode is further in contact with part of the first source contact region, plane gates are arranged on the current diffusion layer and the epitaxial well region, a first base region and a second base region are arranged in the current diffusion layer, the first base region is completely arranged in the second base region, or the first base region is partially arranged in the second base region, and the second base region is arranged in the epitaxial well region. Oscillation of the device in the turn-off process can be reduced while the turn-off speed of the device is increased, the switching loss and electromagnetic interference of the device are reduced, and the problem that a traditional device cannot be balanced between the switching speed and switching oscillation is solved.

The invention relates to a semiconductor chip with double-sided grooves and a manufacturing method thereof. Belongs to the technical field of power semiconductor devices. The problems that an existing single-groove chip is low in production efficiency, high in cost and limited in forward and reverse blocking voltage boosting are mainly solved. The device is mainly characterized in that the trenches are terminal double-sided trenches and are respectively and symmetrically arranged at P-N junction terminals of the N-type substrate, the anode P layer and the cathode P layer, and the inner surfaces of the trenches are provided with protective layers; and cathode P short-circuit points and cathode P + short-circuit points embedded in the cathode P short-circuit points are uniformly arranged in the cathode N + region, so that a low-resistance conductive current channel is formed. According to the invention, the design of a P-type punch-through ring structure is canceled, and the low-concentration P-type doping and high-concentration P + design is adopted, so that the short-circuit punch-through resistance can be reduced, the through-current capability and the blocking voltage of the chip can be improved, and the method is mainly used for manufacturing medium-voltage and high-voltage power semiconductor device chips.