4results about How to "Enhanced conductance modulation effect" patented technology

The present application belongs to the technical field of power semiconductor devices, and relates to a self-bias split gate bipolar transistor and a manufacturing method thereof. The present application provides a bias potential for the split gate (11) through the potential of the floating P region (18), thereby forming the electron accumulation ability below the trench, enhancing the conductance modulation ability, and thus enhancing the forward conduction ability of the device. Compared with the traditional split gate structure, the diode and capacitor structure of the self-bias structure are integrated into the IGBT structure, which can simultaneously improve the conduction ability and switching performance of the device without affecting the device size and IGBT operation, eliminates the negative effects brought by the split gate, improves the switching loss and enhances the switching speed, optimizes the forward conduction ability of the device, and improves the compromise characteristics between the forward conduction voltage drop and the off-state loss of the device.

The application provides a semiconductor device, relates to the technical field of semiconductor, and aims to solve the problem of increased on-resistance caused by bipolar degradation of a semiconductor device in the prior art.The semiconductor device comprises a polycrystalline silicon carbide substrate with P-type conductivity, a drift layer with N-type conductivity, and a collector metal layer, the drift layer is arranged above the polycrystalline silicon carbide substrate, and the drift layer is internally provided with a P column and an N region which are adjacent in the lateral direction; the collector metal layer is directly laminated on the other side of the polycrystalline silicon carbide substrate which is away from the drift layer and forms an ohmic contact with the polycrystalline silicon carbide substrate. The polycrystalline silicon carbide substrate can inject a higher concentration of minority carriers into the drift layer, so as to improve the conductance modulation efficiency and reduce the resistance; meanwhile, the polycrystalline silicon carbide substrate makes the recombination process of electrons and holes in the drift layer more uniform, and energy is not released at a certain point, thereby reducing the serious bipolar degradation phenomenon caused by local defect aggregation.

The present invention relates to a trench-type power device and a preparation method, in particular to a trench-type power device and a preparation method capable of improving breakdown characteristics. According to the technical solution provided by the present invention, a trench-type power device capable of improving breakdown characteristics, the trench-type power device comprises: a semiconductor substrate of a first conductivity type; an active region prepared in the central region of the semiconductor substrate, comprising a plurality of cells connected in parallel, wherein the cells in the active region adopt a trench structure, and the bottom of the trench of the cell trench is located below the second conductivity type base region across the active region; a first conductivity type carrier storage layer is arranged in the second conductivity type base region, and the first conductivity type carrier storage layer contacts the outer side wall of the corresponding cell trench. The present invention improves the breakdown characteristics of the power device, reduces the conduction loss of the power device, increases the switching speed, and effectively reduces the conduction voltage drop.

The present invention provides a trench gate IGBT structure and a semiconductor device, wherein the trench gate IGBT structure comprises: a first trench gate extending from the substrate surface to the N-drift region; a first P-type doped region, the P-type base region and the N-drift region each arranged on one side of the first trench gate, wherein a plug is arranged in the first P-type doped region for grounding; a second trench gate arranged in the first P-type doped region, electrically connected to the first trench gate, and the length of the second trench gate is less than the length of the first trench gate; an N-type floating buried layer arranged in the first P-type doped region below the second trench gate, wherein one end of the N-type floating buried layer is spaced apart from the first trench gate. The present invention can simultaneously optimize the on-state voltage drop and off-state loss of the trench gate IGBT structure.