84results about How to "Enhanced conductance modulation effect" patented technology

The invention discloses an insulate gate bipolar transistor (IGBT) with a current carrier storage layer and an additional hole passage, and belongs to the technical field of semiconductor power devices. In the IGBT, an N-type current carrier storage layer (5) and a large P<+> tagma (4) structure are introduced on the basis of a conventional planar non-pouch-through IGBT. The N-type current carrier storage layer (5) improves a conductivity modulation effect close to an emitter and the large P<+> tagma (4) structure plays a role in providing an additional passage for a hole so that the latch-up resistance is improved. Due to the design of the N-type current carrier storage layer (5) and the large P<+> tagma (4), the flow path of a hole current of the conventional IGBT is optimized, so that a safety operation area of a device is enlarged and the sensitivity of latch current density to a temperature is reduced.

The invention discloses a plane gate type IGBT (Insulated Gate Bipolar Translator) chip production method. The method comprises the steps: firstly carrying out front side processing, and injecting and annealing a second N type current carrier buried layer to a semiconductor substrate; etching, injecting and annealing a first N type current carrier buried layer injection window; etching a first N type current carrier buried layer; removing an oxidization layer on the surface of the semiconductor substrate; depositing an insulating material on the outer surface of the first N type current carrier buried layer, and photoetching and etching the deposited insulating material to form a media buried layer; completing the remaining front side processing technology; conducting back side processing, thinning the back side part to the needed thickness; injecting, doping and propelling and annealing an N buffer layer; injecting, doping and propelling and annealing a P+ collector electrode region; and producing a metal collector electrode. According to the plane gate type IGBT chip production method, the drop voltage of an IGBT chip is reduced, the compromise relation of the turn-off loss can be optimized, and lower power consumption can be realized, so that the power density, operating junction temperature and reliability of the IGBT chip can be improved.

The invention relates to an insulated gate bipolar transistor device with low conduction voltage drop, and a manufacturing method for the insulated gate bipolar transistor device. The device comprises an active region located on a semiconductor substrate, and a terminal protection region. Active cells of the active region on the section of the device employ a trench structure, and comprise active cells and non-active cells. The bottom of an active cell trench and the bottom of a non-active cell trench are respectively provided with a floating region of a second conductive type, wherein the floating region of the second conductive type below the active cell trench wraps the bottom of the active cell trench, and the floating region of the second conductive type below the non-active cell trench wraps the bottom of the non-active cell trench. The device has extremely low conduction voltage drop and extremely quick cut-off speed under the condition that the withstand voltage is guaranteed, is lower in current and voltage oscillation, and greatly improves the work reliability.

The invention discloses a method for manufacturing a trench gate type IGBT (insulated gate bipolar transistor) chip, which comprises the following steps: selecting two N-shaped semiconductor substrates, and carrying out oxidation or deposition on one of the substrates, so that insulating materials including silicon oxides or nitric oxides are formed on the surface of the substrate; carrying out photoetching and etching on the insulating materials on the surface of the substrate so as to form a dielectric buried layer; carrying out photoetching and etching on the other substrates so as to form a figure coincided with the concave-convex surface of the dielectric buried layer; carrying out concave-convex surface butt-joint on the dielectric buried layer and the figure, and bonding the two substrates together at high temperature; according to voltage-withstanding requirements and machining allowances, respectively carrying out thinning processing on the two substrates, and controlling the dielectric buried layer at a design depth, so that a chip manufacturing intermediate is formed; and completing the manufacturing process of a trench gate type IGBT chip. According to the invention, the drop voltage of the chip is reduced, a compromising relation with shut-off loss is optimized, and the lower power consumption is realized, thereby improving the power density, operating junction temperature and reliability of the IGBT chip.

The invention discloses a planar gate IGBT (Insulated Gate Bipolar Transistor) chip, which comprises a collector metal electrode, a P+ collector region, an N- drift region, a P- base region, a P+ ohmic contact region, an N+ source region, a gate oxide layer, a polysilicon gate and a gate metal electrode which are arranged successively, and an emitter metal electrode arranged above the P+ ohmic contact region, wherein the polysilicon gate of the planar gate IGBT chip adopts a planar gate structure. The planar gate IGBT chip also comprises a first N-type carrier buried layer and/or a second N-type carrier buried layer. The first N-type carrier buried layer is located below the P- base region. The second N-type carrier buried layer is located below the gate oxide layer and at both sides of the P- base region. The planar gate IGBT chip has the beneficial effects that the compromise relation between conduction pressure drop and turn-off loss of the IGBT is reduced, lower power consumption is realized, and thus the power density, the operating junction temperature and the long-term reliability of the IGBT chip are increased.

The invention discloses a thyristor gate cathode structure and a gate pole commutation thyristor with the thyristor gate cathode structure. The thyristor comprises an N-substrate, a P base region, a P+ short base region, an N+ emitter region, a door pole metal electrode and a cathode metal electrode. The N+ emitter region, the P+ short base region, the P base region and the N-substrate are sequentially distributed, the cathode metal electrode is arranged on the outer surface of the N+ emitter region, and the door pole metal electrode is arranged on the outer surface of the P+ short base region. The thyristor gate cathode structure is of a two-layer step structure, wherein the first layer of steps is a shallow step, and the bottom of the first layer of the steps is a P+N+ boundary. The second layer of the steps is a deep step, and the bottom of the second layer of the steps is a PN+ boundary. The gate pole commutation thyristor with the thyristor gate cathode structure further comprises an N' buffer layer and a P+ anode region. The combination of electrons injected in the N+ emitter region of the thyristor is reduced at the P+ short base region and the P base region, conductivity modulation effects of the thyristor are intensified, and connected currents and the starting speed can be further improved.

The invention discloses an IGBT device and a manufacturing method thereof. The IGBT device comprises a substrate which comprises a drift region; a grid electrode structure and a source electrode structure which are arranged on the front surface of the substrate, and the source electrode structure comprises a trap region which is arranged in the surface of the drift region and a source region which is arranged in the surface of the trap region; a carrier storage layer which is arranged in the surface of the drift region and below the trap region, a gap is arranged between the carrier storage layer and the bottom part of the trap region, a doping type of the carrier storage layer and the doping type of the drift region are identical and doping concentration of the carrier storage layer is greater than that of the drift region; and a current collection region which is arranged on the back surface of the substrate, and the doping types of the current collection region and the drift region are opposite. The IGBT device is lower in conduction pressure drop and thus is low in conduction loss.

The invention discloses an insulated gate bipolar translator (IGBT) device with two short-circuit positive electrodes, and belongs to the technical field of semiconductor power devices. A positive electrode structure of the device is a two-positive-electrode short-circuit structure. The IGBT device comprises a first P+ hole emission layer, a second P+ hole emission layer, a metal collector and a silicon dioxide barrier layer, wherein the silicon dioxide barrier layer is positioned on the back face of the first P+ hole emission layer; the metal collector is positioned on the side face of the first P+ hole emission layer and below the second P+ hole emission layer, and the two P+ hole emission layers are contacted with each other; the second P+ hole emission layer is positioned at the bottom of an N- drift region and staggered in parallel with the first P+ hole emission layer; and an electronic trench is formed between the first P+ hole emission layer and the second P+ hole emission layer. The positive electrode structure of the IGBT device is improved, so that the hole injection efficiency is improved, the current carrier concentration distribution in the drift region is optimized, the conductivity modulation performance in the device body is improved, a negative differential resistance (NDR) region is eliminated effectively, the cut-off loss of the IGBT device is reduced effectively, and finally, compromise optimization for conductivity pressure drop and cut-off loss is realized.

The invention relates to a charge storage type insulated gate bipolar transistor and a preparation method thereof, belonging to the technical field of power semiconductors. By improving the charge storage layer of the traditional charge storage type IGBT device, a semiconductor material used for the charge storage layer remote from the drift region has a larger band gap than a semiconductor material used for the charge storage layer close to the drift region, so that the semiconductor materials with different forbidden band widths form the same-type heterojunction at their contact interfaces,thereby forming a potential barrier that prevents minority carriers in the drift region from entering the base region. As a result, the carrier distribution concentration in the drift region is improved, the conductivity modulation effect of the IGBT is enhanced, the forward conduction voltage drop Vceon of the device is reduced, the breakdown voltage of the IGBT is optimized, and the tradeoff between the forward conduction voltage drop Vceon and the shutdown loss Eoff is achieved. Moreover, by adjusting the doping concentration of materials with different bandgap widths in the charge storagelayer and the combination of materials with different bandgap widths, the invention can further optimize the working characteristics of the device.

The invention relates to a planar insulated gate bipolar transistor and a preparation method thereof, belonging to the technical field of power semiconductors. A semiconductor layer or Schottky contact metal having a relatively small band gap is introduced into the upper surface of the base region of the device adjacent to the outer side of the emitter region, By using heterojunction or Schottky contact as minority carrier barrier to enhance the conductivity modulation effect, the conduction voltage drop is reduced and the tradeoff between forward voltage drop and turn-off loss is optimized. As the heterojunction or Schottky contact introduced by the invention can replace the CS layer functionally, the electric field strength of the PN junction formed in the base region and the drift region is reduced to improve the breakdown voltage of the device; And the electric field intensity of the gate oxide layer is below the safe value (3MV/cm), so the reliability of the gate oxide layer is ensured. In addition, the fabrication process of the device is simple and controllable, and the device has strong compatibility with the existing process.

The invention discloses an SOI-LIGBT (Silicon on Insulator-Lateral Insulated-Gate Bipolar Transistor) device based on a double channel structure. The SOI-LIGBT apparatus based on the double channel structure comprises a P type substrate, wherein a buried oxide layer is paved on the P type substrate, an N-epitaxial layer is paved on the buried oxide layer, a P+ collector region is embedded on the N-epitaxial layer, and two symmetrical body region structures are arranged in parallel on the N-epitaxial layer on one side of the P+ collector region. Each body region structure comprises a P well arranged on the N-epitaxial layer, an N+ emitter region embedded on the P well and a P+ contact region penetrating through the P well. According to the SOI-LIGBT device based on the double channel structure provided by the invention, two channel regions are arranged at the emitter region so that the cavity current flowing from the collector to the emitter is uniformly divided into two strands of current, therefore, the current flowing through a base electrode of a parasitic NPN triode is reduced to 50% of the total current. A parasitic thyristor is inhibited from being opened and the anti-latch capacity of the device is improved, so that the reliability of the device is improved.

The invention relates to an insulated gate bipolar transistor and a preparation method thereof, belonging to the technical field of power semiconductors. On the basis of the traditional charge storagetype IGBT device structure, A heterojunction structure is formed in the base region, thereby forming a potential barrier that prevents minority carriers in the drift region from flowing into the baseregion, thereby greatly increasing the minority carrier concentration near the emitter side in the drift region, The carrier concentration distribution in drift region is improved and the conductivity modulation effect of IGBT is enhanced, which reduces the forward conduction voltage drop Vceon and optimizes the tradeoff between the forward conduction voltage drop Vceon and the shutdown loss Eoffof IGBT. It overcomes the shortcoming that the traditional charge storage layer reduces Vceon and breakdown voltage at the same time. Moreover, the device performance can be further optimized by adjusting the combination of semiconductor materials with different forbidden band widths to form heterojunction structures.

The invention discloses a groove type IGBT and a manufacturing method. A P type region with heavy doping and an N type region with heavy doping are added in the middle region of a silicon substrate, so that electrons are induced to flow in an N junction region to be concentrated, penetrate through the P type region and finally reach a collector through the P type region. Based on the electric neutrality principle, the concentration of the electrons on the periphery of the N type region is increased due to the concentration of the electrons, the concentration of holes in the periphery of the N type region is increased, so that the conductance modulation effect of the N type region is increased due to the concentration of the electrons, and the holes are diffused to an emitter through the P type region. According to the groove type IGBI manufacturing method, the charge balance principle is utilized, the electric field intensity in the region is increased so that larger voltage can be obtained under the same drift region thickness, the thickness is reduced, the conductance modulation effect is improved, and the conduction voltage drop of a device is effectively reduced.

The invention discloses a semiconductor device having a trench structure. A surface of an N-type conductive semiconductor material is provided with trenches, an entire area of an upper part of the semiconductor material between the trenches is a P-type conductive material area, and a passivation layer is disposed on an upper surface of the P-type conductive material area. The P-type conductive material area is also disposed in the semiconductor material on corners of trench bottom edges. And Schottky barrier junctions are disposed on side walls of the trenches and surfaces of a bottom N-type conductive semiconductor material. The invention also provides a manufacture method for the semiconductor device, and through the manufacture method, a rapid-recovery diode can be made by twice photolithography technique.

The invention provides an insulated gate bipolar transistor, which is manufactured by using a silicon chip. The insulated gate bipolar transistor comprises a P+ region, an N- region, a P region and an N+ region, wherein the P region and the N+ region are positioned on the front surface of the silicon chip; the P+ region is positioned on the back surface of the silicon chip; and the P+ region comprises a plurality of P-type impurity regions which are longitudinally distributed in a doping way. The invention also provides a method for manufacturing the insulated gate bipolar transistor. As the P+ region comprises the plurality of P-type impurity regions to increase the effective area of an emitter and increase injected P-type impurities, cavity minority carriers injected into the N- region are increased, conductivity modulation effect on the N- region is enhanced, the on-state voltage drop of the insulated gate bipolar transistor is reduced and the loss of own power of the insulated gate bipolar transistor is further reduced.

The invention belongs to the technical field of power semiconductor devices and relates to an MOS (Metal Oxide Semiconductor) gated thyristor integrating a Schottky diode. According to the MOS gated thyristor provided by the invention, a device cathode is designed to be in contact with Schottky, so that one Schottky diode is formed between a P trap region and the cathode, wherein the pumping of acharge carrier in a switching-off process can be accelerated by a P+ region, but the pulse performance of the device is not influenced; in a manufacturing process, whether the P+ region is remained ornot can be selected according to requirements. By adopting two structures, the current distribution is more uniform when the device works and the minimum current needed by a latch of the device is reduced; pulse peak value current is further improved under small current and the increasing rate of the current (di/dt) is improved; the time of the device which works under an IGBT (Insulated Gate Bipolar Transistor) mode is shortened; the crystal lattice temperature of the device which works under the IGBT mode at an pulse discharging initial stage of the device is effectively reduced, and furthermore, pulse properties of the device are improved.