42results about How to "Reduce voltage variation" patented technology

In the clamp circuit, the first transistor shifts a target clamp voltage by a gate-source voltage to output the target clamp voltage. The buffer circuit inputs the shifted voltage and output a reference voltage on the inputted shifted voltage. The gate of the second transistor is connected to the output terminal of the buffer circuit. The source of the second transistor is connected to the input terminal of the first transistor. In this structure, the reference voltage is supplied to the gate of the second transistor so that, when a terminal voltage of the input terminal of the IC is not less than a clamp voltage corresponding to the sum of the reference voltage and a threshold voltage of the second transistor, the second transistor turns on, whereby the terminal voltage is clamped to a clamp voltage related to the target clamp voltage.

A digital camera, including a common power supply for supplying power; a plurality of motors sharing the power supply and driven by the power supplied from the power supply; and a current detector for detecting load current supplied to the plurality of motors, wherein, when either one of the plurality of motors is operated, other motor is driven not to overlap with a maximum value of the load current detected by the current detector.

The invention provides an array substrate, a touch display panel and a touch display device. The array substrate comprises grid lines, data lines, pixel units and a public electrode layer, wherein the pixel units are enclosed by the grid lines and the data lines, and the public electrode layer is divided into multiple electrode units. Each electrode unit comprises at least two electrode blocks provided with nested intersection areas, the length of the intersection area in the extending direction of the data lines is larger than or equal to the length of an overlapped area of driving signals along the extending direction of the data lines, and the overlapped area of the driving signals comprises the overlapped grid lines and pixel units electrically connected with the grid lines. Accordingly, coupling mutation degree at the boundary of the adjacent electrode blocks can be lowered, voltage change amplitude of the electrode blocks during cutoff of thin-film transistors of the pixel units of the adjacent electrode block boundary is alleviated, and image display effect is improved.

A power supply apparatus, including a power supply configured to supply power to a plurality of devices or circuits to operate said plurality of devices or circuits; and a moderation mechanism configured to control the power supplied to the plurality of devices or circuits, wherein the moderation mechanism is configured to control the power supplied to the plurality of devices or circuits such that the plurality of devices or circuits does not operate simultaneously at the time when the plurality of devices or circuits initiates its operation or stops.

A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias voltage. When the voltage source used in the controllable delay line has a variation, the second bias voltage varies therewith. The regulation capacitor is used for reducing the variation of the voltage difference between the voltage source and a node voltage of the first current source. The compensation capacitor is used for reducing the influence of a transition of the input signal of the output buffer unit on the node voltage, so as to lower the jitter amount of the output signal of the output buffer unit.

In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n− type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 μm or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm−3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.

A structure and method for damping LC (inductance-capacitance) ringing in integrated circuit (IC) power distribution systems. The structure comprises a resistance electrically connected in parallel with a plurality of electrical switches. The resistance and electrical switches are electrically connected in series with the package and on-chip power distribution circuit. When on-chip switching activity creates a sudden and appreciable change in IC power demand the electrical switches are opened to temporarily increase the resistance in series with the power supply. This serves to dampen the power-distribution LC ringing. Later, the electrical switches are closed to shunt the series resistance and reduce the level of steady-state voltage drop in the power structure.

A liquid crystal display according to the present invention can prevent interference fringe on a display panel due to a switching noise of a DC / DC converter, therefore a high-quality image can be displayed. Either of input signals for a timing control circuit is also supplied to a PLL circuit and the DC / DC converter is controlled by an output signal of the PLL circuit, thereby enables to synchronize a switching frequency of the DC / DC converter and control signal.

The invention provides an insulated gate bipolar transistor (IGBT) driving circuit, which comprises a switching-on resistor with a relatively higher resistance value, a switching-off resistor with a relatively lower resistance value and a switching input circuit, wherein the switching input circuit is connected to the gate of an IGBT by the switching-on resistor; and one end of the switching-off resistor is connected to the gate of the IGBT. The IGBT driving circuit further comprises an over-voltage detection circuit and a rapid switching-off control circuit. The rapid switching-off control circuit controls the other end of the switching-off resistor to be switched off when the switching input circuits inputs a switching-on level, controls the other end of the switching-off circuit to be grounded when the switching input circuit inputs a switching-off level, and controls the other end of the switching-off resistor to be switched off when the voltage, detected by the over-voltage detection circuit, of the collector of the IGBT is higher than a preset value. The IGBT driving circuit provided by the invention can rapidly realize the rapid switching-off of the IGBT and simultaneously suppress the excessive voltage variations of the IGBT.