Semiconductor device and manufacturing method thereof, and electronic apparatus

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and an electronic apparatus. The manufacturing method includes: a semiconductor substrate is provided, front devices of a plurality of memory cells are formed on the semiconductor substrate, each memory cell comprises at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, wherein the pull-up transistors, the pull-down transistors, and the pass-gate transistors all comprise grid electrodes and grid electrode sidewalls, and asymmetric pocket ion implantation is performed for the two pass-gate transistors of each memory cell. According to the manufacturing method for the semiconductor device, the pass-gate transistors in asymmetric pocket areas with different doping concentrations are formed, the conflict between the writability and the reading stability of an SRAM unit can be effectively balanced, the writability and the reading stability of the SRAM unit are improved, and the reliability of the SRAM unit is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor storage, in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important part of digital systems. SRAM (StaticRandomAccessMemory, static random access memory) has become an indispensable and important part of the on-chip memory with its advantages of low power consumption and high speed. SRAM can hold data as long as it is powered, there is no need to constantly refresh it. [0003] The basic SRAM storage unit generally includes six transistors: 2 pull-up transistors PU (Pull-up transistor), 2 pull-down transistors PD (Pull-down transistor), and 2 pass-gate transistors PG (Pass-gate transistor). In the design process of SRAM memory cells, it is usually necessary to ensure a sufficiently large β ratio (Ipd / Ipg curr...

AI Technical Summary

Problems solved by technology

Therefore, the different requirements on the performance of the pass transistors create a conflict between the writeability and read stability of the SRAM cell

And this conflict has always been the bottleneck of traditional 6TSRAM memory cell design

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