56 results about "Gate turn-off thyristor" patented technology

The invention relates to a voltage space vector control device and a voltage space vector control method for soft start. At present, a soft start technology has the problems of high starting current and low starting torque, and frequency converter soft start has the shortcoming of difficulty in the implementation of power frequency switching. A three-phase alternating current power supply is used for supplying power, six electric GTOs (gate-turn-off thyristors) can be reversely connected in parallel, an IGBT (insulated gate bipolar transistor) is adopted for a continuous current circuit, a voltage space vector control circuit is formed under the control of a microcontroller, and a current transformer is used for transmitting a three-phase current signal to the microcontroller for current limiting start and current monitoring. The phases A, B and C of the power supply of a three-phase alternating current asynchronous motor are subjected to alternating current voltage regulation and frequency modulation control under the control of the microcontroller, a voltage space vector control strategy is used for realizing hexagonal flux linkage track control over the alternating current motor, the voltage/frequency ratio is relatively stable, and the stability of main magnetic flux of the motor is ensured.

The method is applicable to manufacture silicon semiconductor binistor with at least one PN junction such as GTO, IGBT etc. General manufacturing steps is carried out till the step of making metalized electrode. Platinum-silicon alloy is made on surface of silicon. Using proton or particle injection forms local high density defect area. Heating and annealing makes the defect area absorb platinum to convert to platinum impurity range. Then, General manufacturing steps is carried out till manufacturing completion. The performances of the invention are better than present life control technique. The parts made by the invention possesses higher switching speed and backward recovery speed, but the forward voltage drop and reverse leakage are not increased visibly.

A mesa-type wide-gap semiconductor gate turn-off thyristor has a low gate withstand voltage and a large leakage current. Since the ionization rate of P-type impurities greatly increases at high temperatures when compared with that at room temperature, the hole implantation amount increases and the minority carrier lifetime becomes longer. Consequently, the maximum controllable current is significantly lowered when compared with that at room temperature. To solve these problems, a p-type base layer is formed on an n-type SiC cathode emitter layer which has a cathode electrode on one surface, and a thin n-type base layer is formed on the p-type base layer. A mesa-shaped p-type anode emitter layer is formed in the central region of the n-type base layer. An n-type gate contact region is formed sufficiently apart from the junction between the p-type anode emitter layer and the n-type base layer, and an n-type low-resistance gate region is so formed in the n-type base layer that it surrounds the anode emitter layer.

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be ON to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn ON. After the at least one IGBT turns ON, the at least one GTO is configured to turn OFF. After a predetermined amount of time, reflecting the post fabrication alteration to the GTO's minority carrier lifetime (e.g. electron irradiation), after the at least one GTO turns OFF, the at least one IGBT is configured to turn OFF. Alternatively, the circuit is used as an inverter switch, where at the command to turn ON is supplied, the at least one IGBT is turned ON, followed by the at least one SGTO. When commanded to turn OFF the at least one SGTO is turned OFF followed by the at least one IGBT. This alternative configuration allows the robust, controllable switching speeds of IGBTs and the superior conduction efficiency of SGTOs. The two configurations mentioned above utilize a wide range of SGTO performance, thus the ability to control the SGTOs turn-off speed by reducing its minority carrier lifetime after the device is processed is of large importance. The efficiency of all uses of the circuit can be optimized with the judicious selection of SGTO minority carrier lifetime and the ratio of active area between the SGTO and IGBT devices. In all cases there is a balance between the time the circuit can achieve hard turn-off without current commutation, the conduction efficiency of the circuit and the maximum amount of controllable current. In all cases both the conduction efficiency of the circuit is higher than an IGBT-only based circuit, and the switching performance is higher than a GTO-only based circuit.

A constant current generator connected between first and second terminals includes a gate turn-off thyristor in series with a resistor; a current limiting component connected between the anode gate and the cathode gate of the thyristor; and a voltage reference connected between the cathode and the cathode gate of the thyristor.

The invention relates to a DSP (Digital Signal Processor) based improved instantaneous detection and control system of a cascaded active power filter. The system comprises a signal shaping and transformation processing circuit, a central data processing circuit, an insulating and driving circuit and a gate turn off thyristor circuit. The system proposes an improved instantaneous detection method based on a dq transformational theory, and fundamental wave positive-sequence components of voltage and current are synchronously extracted through dq transformation; and through coordinate transformation and projection, a current fundamental wave positive-sequence active component is obtained, and three-phase voltage distortion and fundamental wave positive-sequence active current while asymmetry can be detected in real time. In the invention, a high-performance digital signal processing chip is utilized to control a cascaded multi-level active power compensator, thereby the control speed and precision are greatly improved, the device capacity and the voltage class are improved, the stability of the grid is enhanced, and the influence on the running of whole system due to harmonic pollution is avoided.

The invention belongs to the technical field of electricity, discloses a resistance grounding system, and particularly relates to an automatic control resistance grounding system. One end of a neutral-point isolating switch is connected with one end of a neutral-point current transformer, the other end of the neutral-point isolating switch is connected with one end of a power transformer, the other end of the neutral-point current transformer is connected with one end of a thyristor which can be opened and closed, the other end of the thyristor which can be closed is connected with a neutral-point grounding resistance, the other end of the power transformer is connected with a voltage transformer, and two triangle ends of a secondary opening of the voltage transformer is connected with the relay for controlling the opening and closing of the neutral-point thyristor. The automatic control resistance grounding system improves the reliability of medium-voltage power distribution, prevents the occurrence of cable fires, and can be widely applied in 3 to 35kV industrial enterprises and city network power distribution systems.

A family of emitter turn-off thyristors compres a gate turn-on (GTO) thyristor, a first switch, the drain of the first switch being connected to the cathode of the GTO thyristor, and a second switch connected between the gate of the GTO thyristor and the source of the first switch. The first switch consists of a number of paralleled metal oxide semiconductor field effect transistors (MOSFETs). The anode of the GTO thyristor and the source of the first switch serve as the annode and the cathode, respective, of the emitter turn-off thyristor. The emitter turn-off thyristor has four control electrodes; the gate of the GTO thyristor, the control electrode of the second switch, the gate of the first switch, and the cathode of the GTO thyristor.

The invention relates to an SSCB-based coal mine power grid fast fault current limiter which is mainly used for limiting the current of a coal mine power supply network. The fast fault current limiter is connected in series to a power supply line of a coal mine power grid to limit the short-circuit current of the coal mine power grid. The fast fault current limiter comprises a normal flow loop, a fault current limiting circuit, and a fault judging part. The normal flow loop includes a main switch-off loop and an auxiliary switch-off loop. The main switch-off loop adopts a diode bridge rectifier circuit to convert alternating current into direct current for control, and on-off control of the direct-current loop part is realized by an insulated gate bipolar transistor. The auxiliary switch-off loop is a fast switch-off auxiliary loop composed of a resistor, a capacitor and a gate turn-off thyristor, and is used to quickly switch off the normal flow loop. The invention provides an SSCB-based coal mine power grid fast fault current limiter which reduces the short-circuit current in the case of failure to improve the residual voltage of a bus when a coal mine power grid fails and further ensure normal power supply of other lines connected to the bus.

The invention relates to a control system of the bridge type superconducting current limiter bases on the DSP. It treats the circuit through the signal reshaping transformation to collect the electrical signals, send the signal to the power driving tube circuit after being treated by the central data processing circuit, then control the gate-controlled switch element circuit of the bridge type superconducting current limiter and reach the aim to controll the system. The advantages and the technological effects of the invention lie in the following aspects: adopting the DSP to form the control system, simple hardware circuit, highly precise real time control, increased stability and reliability of the system. Appling the DSP to the bridge type superconducting current limiter and carrying out the closed loop control to the electronic switch composed of the GTO and other parts can reduce the loss caused by the short circuit of the electric power.

The highest-power switches now available are based on thyristor-type devices: GTOs (Gate turn-off thyristors), MTOs (MOS controlled turn-off thyristors), IGCTs (Integrated gate commutated thyristors), and the new ETOs (Emitter turn-off thyristors). These devices handle kilovolts and kiloamperes for megawatt inverters/converters. Measurements by the inventors show that conduction losses of MOSFETs and switching losses of IGCTs are drastically decreased by cryo-cooling. IGCTs, ETOs, and MTOs, together with many small, low voltage MOSFETs for gate and emitter turn-off circuitry, are cryo-cooled to attain much higher switching speeds and a reduction in size, weight and cost of high-power (megawatt range) equipment.

The invention discloses a secondary alternating-current resonance elimination device used for an electromagnetic type voltage transformer. The device comprises a fully-controlled switch unit (1) and a discharging resistor (2), and the fully-controlled switch unit (1) and the discharging resistor (2) are connected with the two ends of an open delta winding (3) of the electromagnetic type voltage transformer after being connected in series to form a circuit; the fully-controlled switch unit (1) is composed of two fully-controlled switch devices reversely connected in parallel; each fully-controlled switch device is one of an insulated gate bipolar transistor (IGBT), an integrated gate commutated thyristor (IGCT) and a gate turn-off thyristor (GTO). The secondary alternating-current resonance elimination device is simple in structure, can quickly and effectively suppress ferromagnetic resonance overvoltage generated by the electromagnetic type voltage transformer and does not influence normal and asymmetric operation modes of a system, and accordingly safety and stability of power system operation are effectively improved.

The invention provides a device array of a silicon carbide gate turn-off thyristor GTO and a preparation method thereof, wherein each single device is relatively small in size. The device array is formed by photoetching according to a corresponding photoetching layout and comprises at least two array structures of silicon carbide gate turn-off thyristors. The gate electrode of a GTO device unit islocated in the center of the table surface of the device unit. The gate electrode of the GTO device unit forms an interdigital structure together with anodes located on the two sides of the table surface of the device unit. A cathode is located on the back surface of the substrate of the device unit. During the packaging process, the gate electrodes of all device units are led down to a packagingstructure according to the layout design. Meanwhile, all anodes are led out in the opposite directions of the gate electrodes. According to the device array scheme adopted by the invention, the effective working area of a whole packaging chip can be remarkably improved. The condition that the performance of the whole packaging chip is reduced due to the defects of local materials can be avoided.Moreover, the process difficulty of device machining can be reduced, and the process stability and the process uniformity can be improved. The yield of prepared devices can be remarkably improved.

The invention discloses a secondary direct-current resonance elimination device used for an electromagnetic type voltage transformer. The device comprises a rectifier circuit, a fully-controlled switch device and a discharging resistor. The alternating-current side connection end of the rectifier circuit is connected with the connection end of an open delta winding of the electromagnetic type voltage transformer, and the direct-current side connection end of the rectifier circuit, the fully-controlled switch device and the discharging resistor are connected in series to form a circuit; the fully-controlled switch device is one of an insulated gate bipolar transistor (IGBT), an integrated gate commutated thyristor (IGCT) and a gate turn-off thyristor (GTO); the rectifier circuit is a single-phase uncontrolled rectifier bridge composed of four rectifier diodes. The secondary direct-current resonance elimination device can quickly and effectively suppress ferromagnetic resonance overvoltage generated by the electromagnetic type voltage transformer and does not influence normal and asymmetric operation modes of a system, and accordingly safety and stability of power system operation are effectively improved and the structure is simple.

The invention relates to a power semiconductor technology, in particular to a silicon carbide gate turn-off thyristor. The invention modifies the cathode region of the conventional silicon carbide GTOby adding a layer of N-IEB layer (N-type Injection Enhanced Buffer Layer). As the doping concentration of the IEB layer 13 is low, the lifetime and mobility of minority carriers in the region are improved, and the diffusion length of minority carriers in the cathode structure is increased, thereby increasing the injection efficiency of the cathode. As a built-in electric field is generated between the N-type substrate 2 and the IEB layer 13 as a result of the concentration difference, , and the direction thereof is pointed from the N-type substrate 2 to the N-type substrate 3-IEB layer 13, which prevents minority hole from diffusing from N-IEB layer 13 to the N-type substrate 2, thereby reducing the minority hole diffusion current and further increasing the cathode injection efficiency.

The invention provides a silicon carbide gate-turn-off thyristor. The thyristor is of a PNPN four-layer SiC structure which is arranged on an N+ type SiC substrate; the upper layer is a strip composedof a plurality of repeatedly-arranged upper tube P-type emission regions; the middle layer is composed of an upper tube N-type base region, an upper tube N type thick base region and an upper tube Ntype thick base region bus bar; the upper tube N type thick base region and the upper tube N type thick base region bus bar are crossed or parallel; and the upper surface of the upper tube N-shaped bus bar is connected with a gate pole metal layer. By virtue of the silicon carbide gate-turn-off thyristor provided by the invention, the current density of the periphery can be reduced, and the anti-dI/dt and anti-dV/dt capability can be improved.

The invention discloses a gate pole turn-off thyristor and a manufacturing method thereof. The gate pole turn-off thyristor comprises a first base region, a second base region, a third base region anda fourth base region which are sequentially formed from bottom to top and also comprises positive electrode metal, negative electrode metal and two gate pole metals, wherein the positive electrode metal is formed on a lower surface of the first base region, the negative electrode metal is formed on an upper surface of the fourth base region, the two gate pole metals are formed on an upper surfaceof the fourth base region and are respectively arranged at two sides of the negative electrode metal, the gate pole turn-off thyristor also comprises a first conductive type of heavy-doped buried layers and a first conductive type of heavy-doped injection regions, the injection regions are respectively formed below the two negative electrode metals, the buried layers are formed below the injection regions, the buried layers extend to the third base region from the upper surface of the third base region, and the injection regions penetrate through the fourth base region from the upper surfaceof the four base region. The invention also discloses a manufacturing method of the gate pole turn-off thyristor. The gate pole-turn-off thyristor has the advantages of small conduction voltage drop and specially short turn-off time.

The invention provides a gate-turn-off thyristor. A plurality of strips formed by repeatedly arraying a plurality of high-doping-concentration upper tube N type emission regions are arranged on an upper surface of an N type silicon substrate chip; an upper tube P-type concentrated basic region bus bar is arranged around the periphery of each strip; a cathode metal layer is arranged on the upper surface of one upper tube N type emission region, an upper tube P-type basic region is arranged below the upper tube N type emission region, and a side face of the upper tube P-type basic region is connected with an upper tube P-type concentrated basic region or the upper tube P-type concentrated basic region bus bar; an upper tube N-type current collection region is arranged below the upper tube P-type basic region, the upper tube P-type concentrated basic region and the upper tube P-type concentrated basic region bus bar; a lower tube P-type emission region is arranged below the upper tube N-type current collection region; a lower surface of the lower tube P-type emission region is connected with an anode metal layer; a gate metal layer is arranged above the silicon substrate chip. According to the gate-turn-off thyristor provided by the invention, anti-dI/dt ad anti-dV/dt capabilities of turn-off thyristor are remarkably enhanced, and breakdown voltage and a current capacity have a wide application range.

The invention relates to a storage battery charging control circuit in a photovoltaic power generation system. The positive electrode of a solar cell panel is connected with the anode of a diode. The cathode of the diode is connected with the anode of a thyristor capable of being turned off. The cathode of the thyristor capable of being turned off is connected with the cathode of a voltage stabilizing diode and then connected with one end of an inductor. The other end of the inductor is connected to the anode of a storage battery. The cathode of the storage battery is connected with the anode of the voltage stabilizing diode and then connected with the negative electrode of the solar cell panel. When positive and negative trigger signals are added to the gate pole of the thyristor capable of being turned off, the thyristor capable of being turned off can be automatically turned off, and the charging voltage of the storage battery is adjusted. The storage battery charging control circuit is simple in structure, low in cost and high in reliability.