Semiconductor power device with ultralow power consumption and preparation method

Abstract

The invention discloses a semiconductor power device with ultralow power consumption, wherein the quantity of photo-etching layers is small, and reverse recovery time is short. The device comprises a semiconductor baseplate, wherein a cellular area and a terminal protection area are disposed on the semiconductor base plate; and cells are disposed in the cellular area. The structure of the cellular area comprises a cellular groove, wherein upper conductive polycrystalline silicon layers and lower conductive polycrystalline silicon layers are disposed in the cellular groove; two sides of the upper conductive polycrystalline silicon layers are symmetrically disposed at extension parts which are located on two sides of the lower conductive polycrystalline silicon layers so as to form a cap-shaped structure. At least two voltage partition rings and at least one stop ring are disposed in the terminal protection area. The conductive polycrystalline silicon layer close to a voltage partition groove of the cellular area is electrically connected to a source electrode of the device; the rest conductive polycrystalline silicon layers in the voltage partition groove are suspended; and a Schottky diode is disposed in a transition area which is located between the cellular area and the terminal protection area. The invention also discloses a method which can be used for manufacture of the semiconductor power device with the ultralow power consumption.

Description

technical field [0001] The invention relates to a semiconductor power device and a preparation method thereof, in particular to an ultra-low power consumption semiconductor power device and a preparation method thereof. Background technique [0002] The current ultra-low power semiconductor power device is the same as the ordinary semiconductor power device. It has a parasitic diode connected in parallel with it. The anode of the parasitic diode is connected to the body and source of the power device, and the cathode is connected to the drain of the power device. Therefore, power devices are often used for freewheeling and clamping voltage. During freewheeling or clamping voltage, the parasitic diode is forward-conducting, and the power device is also conducting. The source (anode of the parasitic diode) voltage of the power device is higher than the drain ( The cathode of the parasitic diode) has a slightly higher voltage, and the current flows from the source to the drain;...

AI Technical Summary

Problems solved by technology

However, the fly in the ointment is that due to the introduction of the field plate structure of the shielded gate in the device structure, the device structure and process are more complicated, resulting in an increase in process levels. At present, it is mainly realized by 7-layer photolithography process.

Moreover, the shielded gate is connected to the source on the terminal guard ring, and the electric field is mainly concentrated inside the first guard ring near the cell area during the reverse withstand voltage, resulting in a low withstand voltage

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