Silicon chip carrier with conductive through-vias and method for fabricating same

Abstract

A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Description

FIELD OF THE INVENTION [0001] The invention relates generally to a carrier for mounting and packaging multiple integrated circuit chips; and, more particularly, to a self-supporting semiconductor or insulator carrier substrate with conductive through-vias. BACKGROUND OF THE INVENTION [0002] A carrier for integrated circuit devices is typically fabricated of semiconductor, glass, or glass-ceramic material as a freestanding substrate, chip or wafer having conductive through-vias. The through-vias are exposed on the top and underside of the carrier and are insulated from each other. Multiple levels of carrier material with metallic or semi-metallic vias are often required to obtain the necessary conductive paths between chips and other devices mounted with respect to the carrier. The carrier having through-vias provides chip input / output terminals (I / O), with the chips typically mounted in the “flip chip” manner, and other device I / O through the carrier from the surface at which the ch...

AI Technical Summary

Problems solved by technology

Problems have arisen in carriers of the prior art due to limitations in materials, deposition methods, control of dimensional tolerances, and mechanical stresses encountered during processing of the materials.

As SOC integration density demands increase and speed continues to increase, power densities become untenable.

Current packaging technologies are limited in interconnect density, I / O density, interconnect bandwidth, and chip-to-chip spacing required to reach the ultrahigh performance levels needed, including greater than 10 GHz chip-to-chip communications with full memory bandwidth for >1000 I / Os per chip-to-chip edge interconnection.

It is not possible for current off-chip devices to respond at the on-chip frequencies needed, due to excessive distances from the chip, high parasitic impedance, and slow characteristics of the devices themselves.

Filling high aspect ratio vias, with a height in the range of a single μm to several hundred μms with diameters of several 10's to ˜100 μm, to provide packages with through-vias, is challenging.

However, the hydrodynamics, the ionic concentrations, and the diffusivities limit the filling of deep blind holes.

(ECTC 2002) did extensive plating optimization and were still not able to eliminate voids in vias of only 70 μm deep.

Methods for filling large blind holes which are to be opened later break down or become impractical at such dimensions.

The Black method provides adequate fill of the through-vias (for some of the listed materials); however, given the materials used, the resulting structure will experience the mechanical failures described below with reference to Table 1.

Gaul utilizes materials that are more closely thermally matched, namely W and poly-Si, but would not have practical deposition methods for multi-10's of pin and would have vastly differing values for modulus.

It is also to be noted that incorporation of embedded components into present carriers is difficult due to processing limitations, such as high temperature sintering conditions for ceramic carriers, as well as limitations with embedded component material systems.

At the above-stated diameters, most metals which are commonly used for integrated circuit interconnect vias generate unacceptable stress levels on the carrier layer material (e.g., Si or glass) due to thermal expansion mismatch.

In addition, the metal structures exhibit top surface extrusions, ruptures, or expansions during and after typical thermal cycling.

For carrier substrates and integrated devices that are comprised of brittle materials, such as semiconductors, glass, or ceramics, the risk of mechanical failure by brittle fracture is significant given the thermal expansion mismatches and the fragility of the carrier materials.

In addition to brittle fracture, interfacial delamination is likely when employing standard materials and combinations of materials at the stated dimensions.

However, the modulus of W is so high (>400 GPa) compared to that of silicon (˜170 GPa) that brittle fracture of the Si and / or delamination of via sidewalls are likely, given the finite but small thermal expansion mismatch.

Like W, the typical processes used to grow or deposit poly-Si are only practical for thicknesses up to ˜1 or several single μm, and often are limited to deposition temperatures above the maximum temperatures that can be tolerated by integrated circuit components or wiring on the substrate above (if these are to be fabricated prior to filling the through-vias).

Three potential problems associated with large CTE mismatches between vias and the Si substrate include delamination at the via sidewalls (resulting in so-called “rattling vias” that exhibit compromised conductivity and mechanical stability), cracking of the Si substrate between vias, and piston-like ruptures of any overlying or underlying structures or thin films in contact with the top and bottom surfaces of the vias.

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