85 results about "Parasitic impedance" patented technology

A VCSEL array device formed of a monolithic array of VCSELs and short circuited mesas is disclosed. The VCSELs can be spaced symmetrically or asymmetrical, in a manner to improve power or speed, or in phase and in parallel. The VCSELs are connected to a first metal contact pad formed on a heat-spreading substrate. The short-circuited mesas are formed alongside the VCSELs and are bonded to and form a short circuit to a second metal contact pad on the grounding substrate. Each VCSEL is encompassed by a thick metal heat sink to increase the height of VCSEL mesas. The structure of the heat sink, the VCSELs and the shorting mesas reduce parasitic impedance thereby increasing output power and high frequency response. The VCSELs and shorting mesas can be packaged as a coplanar waveguide in a ground-signal-ground configuration that improves signal modulation characteristics.

A cost-effective, ultra-compact, hybrid power module packaging system and method for making allows device operation in conventional and high temperature ranges over 300° C. Double metal leadframes are directly bonded to the front- and backside of semiconductor chips, and injection-molded high temperature polymer materials encapsulate the module. The invention eliminates the use of unreliable metal wirebonds and solders joints, and expensive aluminum nitride ceramic substrates commonly used in conventional and high temperature hybrid power modules. Advantages of the new power modules include high current carrying capability, low package parasitic impedance, low thermo-mechanical stress under high temperature cycling, low package thermal resistance (double-side cooling), modularity for easy system-level integration, and low-cost manufacturing of devices compatible with current electronic packaging industry. A first embodiment uses molybdenum leadframes for operation in temperatures over 300° C.; a second embodiment of the invention, uses copper and copper alloy leadframes, provides benefits for conventional temperature electronics.

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Using side-wall conductor leads deposited on the side-walls of a base substrate to form package level conductor leads for active circuits manufactured on silicon substrate(s) stacked on the base substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

This document discusses, among other things, a protection system and method configured to detect a parasitic impedance between first and second pins of a standard connector and to remove a current path between a power source and a supply pin of the standard connector if a low-impedance is detected, in certain examples, without adding a current sense resistance to a return path between a ground pin of the standard connector and the power source.

A voltage controlled oscillator including an RF output terminal and a DC control terminal, an active circuit, and a resonant circuit interconnected with the active circuit and including a plurality of series resonators each having an electrically variable capacitance and fixed inductor; the active circuit includes at least one transistor having an operating current density which is approximately 35% or less of the peak f_T operating current density and/or the active circuit includes a multi-transistor bank disposed in at least two separate sections, each pair of sections spaced apart to provide improved thermal uniformity among the transistors without substantially increasing parasitic impedance among them for providing an improved lower phase noise output at said RF output terminal.

The invention provides a method of analyzing a source current at a higher speed and an enhanced accuracy in a semiconductor integrated circuit including a digital circuit. The method to analyze a waveform of the source current, with consideration of re-distribution of charges throughout the digital circuit in the semiconductor integrated circuit, expressing the digital circuit with series of parasitic capacitors ΣC_{ch, ↑} (nT) and ΣC_{ch, ↓} (nT) to be charged and connected between the source and the ground lines. The capacitor series are calculated in time series based on the distribution of switching operations of the logic gates included in the digital circuit. An analysis model for determining the waveform of the source current in the digital circuit is obtained by connecting the parasitic capacitor series with a couple of respective parasitic impedances Z_d and Z_g of the source line and the ground line.

A suppression method for suppressing a via stub effect of a substrate is disclosed. The suppression method is applicable to a substrate having a via, a first conductive line and a second conductive line connected through the via to the first conductive line. The suppression method includes changing a first width of a first conductive segment of the first conductive line connected to the via, and changing a second width of a second conductive segment of the second conductive line connected to the via, so as to change impedances of the first conductive line and the second conductive line to match with a stub impedance of the via, reduce a parasite impedance of the via stub, reach an impedance match at a designed frequency point, and improve an integrity of a signal after traveling from the first conductive line, the via and the second conductive line.

An integrated circuit oscillator includes a microelectromechanical (MEM) resonator having input and output terminals. An oscillation sustaining circuit is provided. The oscillation sustaining circuit is electrically coupled between the input and output terminals of the microelectromechanical resonator. The oscillation sustaining circuit includes a sustaining amplifier and a negative impedance circuit electrically coupled to the sustaining amplifier. The negative impedance circuit is configured to increase a tuning range of the oscillator by at least partially cancelling a parasitic shunt capacitance associated with the microelectromechanical resonator.

A receiver optical subassembly for transforming received optical signal into electrical signal includes at least a ceramic substrate, a photo receiver and a transimpedance amplifier. There are high-speed traces formed on the substrate. The positive and negative pads of the photo receiver are coplanar and connected to the traces without wire bonding so as to reduce the parasitic impedance effect and improve the high-speed performance of the optical subassembly. The transimpedance amplifier is electrically connected to the traces via flip chip, wire bonding or other methods. The photo receiver and the transimpedance amplifier are connected via the high-speed traces formed on the substrate.

Using side-wall conductor leads to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of die-scale surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

The present invention regards a device intrinsically designed to resonate, suitable for RF power transfer, particularly usable for the production of plasma and electrically connectable downstream of a radio frequency power supply with fixed or variable frequency, comprising at least one inductive element (Lp), which can be powered, during use, by such at least one power supply; at least one capacitive element (Cp) electrically connected at the terminals of such at least one inductive element (Lp); such at least one device having a resonance angular frequency equal to: ωo=1/√LpCp. The capacitive element (Cp) and the inductive element (Lp) have values such that, at resonance state, they provide an equivalent impedance, measured at the terminals of such device, substantially of resistive type and much greater than the value of the parasitic impedance upstream of such terminals of such device, such that the effect of such parasitic impedance is, during use, substantially negligible.

An integrated circuit is combined with a transponder to function either as a voltage or power supply for the transponder by extracting energy out of an electromagnetic field transmitted by a base station or as a detector in the transponder to act as a remote sensor. For this purpose the integrated circuit comprises diode rectifiers. Each of the diode rectifiers has a first and a second service terminal and a reference terminal. In order to reduce a parasitic impedance between the first service terminal and the reference terminal, the first service terminal of at least one rectifier diode is electrically connected to a reference potential such as ground. Parasitic diode characteristics are further reduced by surrounding the respective diode or diodes by an electrical conductor path also connected to the reference potential.