34 results about "Parasitic impedance" patented technology

The invention discloses a readout circuit and a readout system for image sensing and solid-state imaging equipment, and relates to the technical field of image sensing readout, and the readout circuit comprises a pixel array unit which is used for photoelectric signal conversion; a current mirror circuit unit; wherein the current mirror circuit unit comprises a cascode current mirror or two N-channel field effect transistors; a negative impedance conversion unit; and a charging and discharging acceleration unit. According to the invention, the negative impedance conversion unit and the charging and discharging acceleration unit are utilized, and the negative impedance generated by the negative impedance conversion unit is counteracted with the parasitic impedance influencing the VSL establishment speed, so that the small signal establishment speed is accelerated; the charging and discharging acceleration unit is used for selectively providing charging and discharging current in the VSL descending establishment process or the VSL ascending establishment process, so that the large signal establishment speed is accelerated. In this way, corresponding response cooperation can be carried out for the VSL descending establishment process or the VSL ascending establishment process.

The invention discloses a readout circuit, a readout system and solid-state imaging equipment, and relates to the technical field of image sensor imaging reading, and the readout circuit comprises a current mirror circuit unit; a negative impedance conversion circuit unit; and a charging and discharging acceleration circuit unit. By configuring the negative impedance conversion circuit unit and the charging and discharging acceleration circuit unit, on one hand, the negative impedance conversion circuit unit can utilize a source follower of the negative impedance conversion circuit unit and a connection mode of related circuit elements, an operational amplifier is not needed, and corresponding negative impedance can be generated to counteract parasitic impedance of the VSL; therefore, the small signal establishment speed is effectively accelerated. The defects that in the prior art, the dynamic range of the VSL is easily limited by increasing the bias current of the load current source circuit, and the performance of the circuit is easily deteriorated due to the fact that the VSL is reduced to a certain degree are effectively overcome. And on the other hand, the charging and discharging acceleration circuit unit provides a large transient current so as to accelerate the large signal establishment speed.

The invention discloses a quantitative compensation calculation method for silicon carbide MOSFET multi-chip parallel current sharing and a related device, and the method comprises the steps: constructing an equivalent circuit model of a multi-chip parallel MOSFET, and extracting the equivalent parasitic parameters of an interconnection structure in a packaging structure; dividing the equivalent circuit model into a drain parasitic impedance network, a gate parasitic impedance network and a source parasitic impedance network; calculating compensation parameters of a drain parasitic impedance network, a gate parasitic impedance network and a source parasitic impedance network according to the equivalent parasitic parameters of the interconnection structure; and respectively compensating the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network according to the compensation parameters of the drain parasitic impedance network, the gate parasitic impedance network and the source parasitic impedance network. According to the method and the related device, quantitative compensation of parallel current sharing of multiple chips of the silicon carbide MOSFET can be realized.

The present invention provides a pixel sensing device and a panel driving device for sensing characteristics of pixels. The present invention provides a technique in pixel sensing, in which a parasitic impedance formed on a sensing line does not affect an integration circuit by using a current mirror circuit coupled with an operational amplifier.

The invention relates to a short line matching microwave transmission structure for a high-temperature superconducting quantum voltage standard, and the structure comprises a transmission matching structure which comprises a bonding wire group and a matching network; the bonding wire group is respectively connected with the coplanar waveguide and the matching network, parasitic impedance is introduced, and the parasitic impedance and initial load impedance of the coplanar waveguide form composite load impedance; the coplanar waveguide is used for transmitting a microwave signal to the Josephson junction array, and quantum voltage is generated through coupling; wherein the matching network is used for receiving a microwave signal and comprises an adjusting assembly, and the adjusting assembly is used for adjusting a capacitance value and / or an inductance value of the matching network, so that the matching network realizes impedance matching between input impedance and composite load impedance under the microwave signal in a preset frequency range. The power entering the junction array chip and the uniformity of the microwave amplitude are improved, and the output quality of the junction is improved.

A high power density integrated circuit module packaging method and its packaging structure belong to the field of microelectronic device packaging technology. In the inner cavity assembly area of the ceramic packaging shell, the chip assembly area is provided with a heat sink area and a functional area, the heat sink area and the functional area are provided as flat bottom pits, the power of the chips in the circuit is graded, a two-stage or more stepped structure is adopted, the chips are distributed from deep flat bottom pits to shallow flat bottom pits according to the power from large to small, the heat sink area is lower than the functional area, the power type chip with large power is assembled in the heat sink area, and the functional type chip with small power is assembled in the functional area. A metal through hole penetrating through the ceramic base body is arranged below the heat sink area or the functional area to realize shortest path heat dissipation and shortest path internal and external electrical connection. The problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of the existing high-power devices (assemblies or modules) are solved. It is widely used in the field of high-reliability power integrated circuit module integration technology.

The invention relates to the technical field of semiconductors, and discloses a metal clamp and a lateral local carrier lifetime control method, and the metal clamp comprises a bracket which is used for accommodating a power device; the metal baffle is located in the bracket, a containing space is formed between the metal baffle and the bracket, the metal baffle comprises a step baffle, the height of a plurality of steps in the step baffle is determined by the target irradiation dose of a corresponding area in the power device, and the plurality of steps are non-obtuse-angle steps. On the basis of not changing the structure of the power device, the radiation dose penetrating through the metal is regulated and controlled through the stepped metal baffle plate, so that the service lives of minority carriers in different regions of the power device are finely designed, the switching-off speeds of the different regions of the power device are different, and the switching-off efficiency of the power device is improved. And turn-off inconsistency caused by parasitic impedance is offset, and turn-off current sharing and turn-off capability improvement are realized.

The utility model discloses a readout circuit, a readout system and a solid-state imaging device, and relates to the technical field of image sensor imaging reading. A negative impedance conversion circuit unit; and a charging and discharging acceleration circuit unit. By configuring the negative impedance conversion circuit unit and the charging and discharging acceleration circuit unit, on one hand, the negative impedance conversion circuit unit can utilize a source follower of the negative impedance conversion circuit unit and a connection mode of related circuit elements, an operational amplifier does not need to be used, and corresponding negative impedance can be generated to counteract parasitic impedance of the VSL; therefore, the small signal establishment speed is effectively accelerated. The defects that in the prior art, the dynamic range of the VSL is easily limited by increasing the bias current of the load current source circuit, and the performance of the circuit is easily deteriorated due to the fact that the VSL is reduced to a certain degree are effectively overcome. And on the other hand, the charging and discharging acceleration circuit unit provides a large transient current so as to accelerate the large signal establishment speed.

The utility model discloses a surface-mounted power hybrid integrated circuit module packaging structure, and belongs to the technical field of microelectronic device packaging. The packaging structure is packaged by adopting a ceramic shell and a metal assembly; a high-power chip and a low-power chip are integrated in different areas in a packaging cavity of a ceramic shell, the integration areas of the high-power chip and the low-power chip are in a step type, the low-power chip and the high-power chip are sequentially integrated from an upper step to a lower step, and seamless isolation and staggered-layer integration are carried out; the high-power chip is sintered on the heat sink, and the heat sink penetrates through the ceramic shell to realize internal and external electric connection; a TU1 material is used in a key parasitic parameter generation area of the packaging structure and penetrates through the ceramic cavity and the outside, and penetrating type connection is achieved. The surface-mounted high-power chip module packaging structure solves the problems of high parasitic impedance, low heat dissipation efficiency, low product power density, low integration level and large packaging size in the conventional surface-mounted high-power chip module packaging structure. The packaging structure is widely applied to the packaging technology of the power hybrid integrated circuit module.

The invention relates to a sensor system and to a method for operating the sensor system, comprising a readout circuit for a capacitive differential sensor output for detecting an analog sensor output signal, the readout circuit comprising at least a capacitance-to-voltage converter and a compensation device for compensating for at least one parasitic impedance, the capacitance-to-voltage converter has a converter input, and wherein the capacitance-to-voltage converter detects the sensor output signal at its converter input as an analog sensor output signal not only under the influence of the at least one parasitic impedance but also under the influence of the compensation device, the compensation device provides a further impedance component at the converter input, which further impedance component at least partially compensates for the influence of the parasitic impedance.

An LCR meter that uses a high-speed balancing method and can balance voltage measurement with only one unit. The LCR meter uses time-separated measurements of the device under test (DUT) and other parasitic component impedances (including leakage impedance) to speed up the balancing. The LCR meter is used to speed up balancing, separation of the measurement time of the device under test (DUT), and other parasitic impedances including leakage impedance. The leakage impedance and other parasitic impedances of the fixture and the LCR meter are measured during open / short calibration and stored in memory. The DUT is measured during measurement using known parasitic impedances. This makes it possible to calculate the balance condition with only one measurement of voltage.

The utility model provides an interactive environment monitoring tag for storage. The interactive environment monitoring tag comprises a viscous substrate, a radiation structure arranged on the upper surface of the viscous substrate, and a radio frequency chip. When the radiation structure receives an external radio frequency identification signal, the radio frequency chip induces the signal to trigger the chip to modulate the radiation structure to output a feedback signal, so that identification data stored in the chip is radiated to the outside. According to the invention, the surface of the radiation structure is coated with the sensitive material, and the sensitive material can correspondingly adjust the parasitic impedance state of the radiation structure according to the storage environment, thereby superposing the modulation information responding to the environmental parameters on the radio frequency signal radiated by the radiation structure. Therefore, the receiving terminal obtains the real-time environment parameters of the storage environment of the goods through the interaction of the radio frequency identification signals. According to the invention, the radio frequency identification tag can be directly reused for the detection and interaction of the environmental parameters, and the sensing detection unit in the storage environment does not need to be independently arranged, so that a simpler, more convenient and more flexible storage environment detection scheme can be provided.

The utility model provides a glass substrate structure and a chip packaging structure, the glass substrate structure comprises at least two glass substrates, the two adjacent glass substrates are electrically connected through a conductive circuit and / or a conductive through hole, the traditional complex process of prefabricating a middle rewiring layer is abandoned, and the production cost is reduced. Through direct stacking without an intermediate layer between glass substrates and interconnection of conductive through holes / circuits, a three-dimensional packaging structure is realized, so that parasitic impedance brought by an intermediate layer is eliminated, interlayer thermal resistance is reduced, and signal transmission efficiency is optimized. Meanwhile, the packaging structure is filled with the conductive paste, the thermal expansion coefficient of the conductive paste is matched with the height of the glass substrate, interface thermal stress is reduced, layering failure under high-temperature circulation is avoided, and the reliability of the packaging structure is improved. And moreover, the conductive circuit and the conductive through hole are filled in a hole groove and slurry manner, so that the defect-free forming of the high-aspect-ratio through hole is realized, and the transmission loss of a high-frequency signal is reduced.

A method and pulsed field ablation (PFA) system configured to provide variable impedance paths for delivery of electric fields to patient tissue using a PFA catheter are disclosed. According to one aspect, a method includes determining a current for each of a plurality of circuit paths, each circuit path including two electrodes. Each current may be determined based at least in part on: a desired voltage between the two electrodes; a tissue impedance between the two electrodes; and a parasitic impedance associated with the circuit path. The method also includes determining at least one of an excitation voltage and an input resistance for each circuit path of the plurality of circuit paths based at least in part on the determined current for the circuit path, parasitic impedances associated with the circuit path and a tissue impedance between the two electrodes in the circuit path.

In one described example, a circuit includes a switching converter comprising a switch with a first current input, a second current input, and a control input, each of the first and second current inputs having an associated parasitic impedance. An energy harvesting circuit has a third input and a first output, the third input being coupled to each of the first and second current inputs. A voltage regulator has a fourth input and a second output, the fourth input being coupled to the first output or an input voltage terminal, and the second output being coupled to a voltage terminal of the circuit.

A wearable electronic device may include: a housing including a first surface, a second surface opposite to the first surface, and a side surface surrounding the first surface and the second surface; a first electrode and a second electrode arranged on the second surface; a third electrode and a fourth electrode arranged on the side surface; and a processor, including processing circuitry, operatively connected to the first electrode, the second electrode, the third electrode, and the fourth electrode. The processor may: repeatedly identify a parasitic impedance value of at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode at designated time points; if the parasitic impedance value of the at least one electrode exceeds a designated first value, identify a resistance value of at least one of the third electrode and the fourth electrode; if the resistance value of at least one of the third electrode and the fourth electrode is less than or equal to a designated second value, identify whether at least one of the third electrode and the fourth electrode is short-circuited; and if a short circuit has occurred in at least one of the third electrode and the fourth electrode due to a conductor, deactivate some functions of the wearable electronic device.

This disclosure is directed to a system and method for applying machine learning model to a PCB layout to obtain an estimate of the parasitic values of the board. The machine learning model may be trained with various PCB layouts to accurately determine an estimated parasitic impedance. Determine regions of the board having a high parasitic impedance value, alerting the user to reconfiguring the region so to achieve a desired range of values.

The present invention discloses a readout circuit, a readout system, and a solid-state imaging device for image sensing, relating to the field of image sensing readout technology, and includes a pixel array unit for photoelectric signal conversion; a current mirror circuit unit; wherein the current mirror circuit unit includes: a common-source common-gate current mirror or two N-channel field-effect transistors; a negative impedance conversion unit; and a charge-discharge acceleration unit. The present invention utilizes a negative impedance conversion unit and a charge-discharge acceleration unit, and uses the negative impedance generated by the negative impedance conversion unit to offset the parasitic impedance that affects the VSL establishment speed, thereby accelerating the small signal establishment speed; and uses the charge-discharge acceleration unit to selectively cooperate with the VSL falling establishment process or rising establishment process to provide charge and discharge current to accelerate the large signal establishment speed. That is, the present application can respond and cooperate with the VSL falling establishment process or rising establishment process accordingly.

The invention relates to the technical field of sewer environmental protection detection, and discloses a sewer environmental protection detection method based on data processing. Four probe electrodes are arranged in the pipeline at equal intervals in the axial direction, parasitic impedance of an instrument and a wire is automatically calculated and compensated through open circuit and short circuit testing, meanwhile, under the preset temperature and humidity condition, sinusoidal signals are sequentially output according to the set frequency range and discrete frequency points, and voltage and current data are collected multiple times after a steady state is waited; eliminating abnormal values lower than a threshold value, counting an average and a variance, and correcting impedance by applying a compensation parameter; three-point linear smoothing is carried out on the corrected impedance, the adjacent consistency is verified, an orthogonal basis function is generated through a self-created discrete Gram-Schmidt algorithm, a pollution-free baseline medium is used for obtaining an expansion coefficient for multiple times so as to dynamically calibrate the health state, and a maximum deviation threshold value is set; in actual detection, real-time impedance is projected on an orthogonal basis, deviation is calculated, and pollution or blockage is rapidly and accurately judged.

In a described example, a circuit includes a switching converter comprising a switch having a first current input, a second current input, and a control input, a respective one of the first current input and the second current input having an associated parasitic impedance. An energy capture circuit has a third input and a first output, in which the third input is coupled to the respective one of the first current input and the second current input. A voltage regulator has a fourth input and a second output, in which the fourth input is coupled to the first output or an input voltage terminal, and the second output is coupled to a voltage terminal of the circuit.

The application discloses a kind of readout circuit, readout system and solid-state imaging device, it is related to image sensor imaging reading technical field, comprising: current mirror circuit unit;Negative impedance conversion circuit unit;Charge and discharge acceleration circuit unit.The application is configured with negative impedance conversion circuit unit and charge and discharge acceleration circuit unit, on the one hand, using the connection mode of the source follower and its related circuit elements of negative impedance conversion circuit unit, without using operational amplifier, corresponding negative impedance and VSL parasitic impedance can also be generated to offset, thereby effectively accelerating small signal establishment speed.Effective to solve the shortcomings of the prior art, such as the limited dynamic range of VSL caused by increasing the bias current of the load current source circuit, which can cause the performance of the circuit to deteriorate when VSL is reduced to a certain extent.On the other hand, a larger transient current is provided by the charge and discharge acceleration circuit unit to accelerate the establishment speed of large signals.

The invention relates to a switching energy capture circuit. In described examples, a circuit (100) includes a switching converter including a switch (102) having a first current input, a second current input, and a control input, a respective one of the first current input and the second current input having an associated parasitic impedance. An energy capture circuit (124) has a third input and a first output, wherein the third input is coupled to the respective one of the first current input and the second current input. A voltage regulator (132) has a fourth input and a second output, where the fourth input is coupled to the first output or input voltage terminal, and the second output is coupled to a voltage terminal of the circuit.

A sensor system and a method for its operation are proposed, comprising a readout circuit for a capacitive differential sensor output for detecting an analog sensor output signal, wherein the readout circuit comprises at least --- a capacitance-voltage converter and --- a compensation device for compensating at least one parasitic impedance includes, wherein the capacitance-to-voltage converter has a converter input and wherein the capacitance-to-voltage converter detects the sensor output signal at its converter input under the influence of both the at least one parasitic impedance and the compensation device as an analog sensor output signal, wherein the compensation device provides a further impedance component at the converter input which at least partially compensates for the influence of the parasitic impedance

A sensor system. The sensor system includes a readout circuit for a capacitive differential sensor output for acquiring an analog sensor output signal. The readout circuit includes: a capacitance-voltage converter, and a compensation device for compensating at least one parasitic impedance; whereinthe capacitance-voltage converter includes a converter input and wherein the capacitance-voltage converter acquires the sensor output signal at its converter input as an analog sensor output signal under the influence of both the at least one parasitic impedance and the compensation device, wherein the compensation device provides a further impedance component at the converter input which at least partially compensates the influence of the parasitic impedance.

The invention provides a semiconductor device radio frequency modeling method and model for a silicon-on-insulator (SOI) platform. The method comprises the following steps: constructing an equivalent circuit model comprising a gate / body end parasitic impedance network, an intrinsic capacitance module, a body resistance module and a substrate network module; an intrinsic capacitance parameter is extracted through a low-frequency CV test, Cg is decomposed into overlapping capacitance, depletion capacitance and accumulation capacitance, and a hyperbolic tangent function and polynomial correction are introduced; extracting parasitic resistance inductance by using layout information and square resistance; bulk resistance parameters modulated by voltage are extracted based on the high-frequency S parameters, and the body resistance is fitted by adopting an exponential function. The model provided by the invention can accurately reflect the back gate effect and the bulk resistance modulation effect of the SOI device, and shows excellent fitting precision in a wide frequency band, wide voltage and wide temperature range.

The invention relates to the technical field of lithium ion testing, and discloses an electrochemical impedance spectroscopy-based lithium battery SOH fault monitoring method, which comprises the following steps of: firstly, acquiring a reference interface roughness parameter and a reference area amplification coefficient in a fault-free state under a set testing condition; applying an alternating current excitation signal to the lithium battery to be detected and collecting original impedance data; obtaining a de-noised interface impedance spectrum after high-frequency parasitic impedance stripping and de-noising reconstruction; a target frequency band with constant phase angle response is locked by calculating a derivative value of an impedance phase angle changing along with frequency; extracting an evolution slope of an imaginary part value in the frequency band, calculating a current interface roughness parameter and converting the current interface roughness parameter into a current area amplification coefficient; and finally, calculating a deviation value with a reference coefficient, and comparing the deviation value with a judgment threshold to output a monitoring result.

A measurement circuit (300) is provided. The measurement circuit (300) includes a control engine (320). An excitation source (302) is coupled to the control engine (320). A first electrode set (322, 326) and a second electrode set (324, 328) are coupled to the excitation source (302) and receive current from the excitation source (302). The control engine (320) operates the excitation source (302) in a first mode and a second mode. In the first mode, the control engine (320) measures a parasitic impedance associated with the first electrode set (322, 326) and the second electrode set (324, 328), and in the second mode, the control engine (320) measures an impedance of the first electrode set (322, 326) and the second electrode set (324, 328) and an impedance of an external object (350).

The invention belongs to the field of integrated circuit testing, particularly relates to a multi-channel analog switch on-resistance testing device and method, and aims to solve the problems that accurate measurement cannot be performed and multi-channel testing requirements cannot be met in the prior art. The system comprises a first power supply measuring unit, a second power supply measuring unit, a plurality of double-pole double-throw relays, a digital vector generating unit, a relay driving control unit and a direct-current voltage source. High-side output and a detection line of the power supply measuring unit are led to the root of a to-be-measured channel pin through a double-pole double-throw relay, and all low-side lines and reference ground are independently connected to the root of a to-be-measured circuit grounding end pin and are converged to form Kelvin connection, so that the influence of parasitic impedance is effectively eliminated, and the reliability of the device is improved. Therefore, high-precision and automatic testing of the on-resistance of the multichannel analog switch is realized.

According to various embodiments, an electronic device may comprise: a biological body contact circuit including four electrodes; a current-voltage measurement module including a power supply port, a current measurement port, a first voltage measurement port, a second voltage measurement port, an alternating current signal generator electrically connected to the power supply port, an ammeter electrically connected to the current measurement port, and a voltmeter interposed between and electrically connected to the first voltage measurement port and the second voltage measurement port; a processor; a memory electrically connected to the processor to store the characteristic impedance values of circuit elements interposed between and electrically connected to the current-voltage measurement module and the biological body contact circuit, and to store values for parasitic impedance stemming from parasitic elements existing between the biological body contact circuit and a ground; and a current-voltage path configuration module configured to electrically connect the biological body contact circuit to the power supply port, the current measurement port, the first voltage measurement port, and the second voltage measurement port such that the voltage path and current path of the biological body contact circuit can be changed under control of the processor. Various other embodiments are also possible.

A method and pulsed field ablation (PFA) system configured to provide variable impedance paths for delivery of electric fields to patient tissue using a PFA catheter are disclosed. According to one aspect, a method includes determining a current for each of a plurality of circuit paths, each circuit path including two electrodes. Each current may be determined based at least in part on: a desired voltage between the two electrodes; a tissue impedance between the two electrodes; and a parasitic impedance associated with the circuit path. The method also includes determining at least one of an excitation voltage and an input resistance for each circuit path of the plurality of circuit paths based at least in part on the determined current for the circuit path, parasitic impedances associated with the circuit path and a tissue impedance between the two electrodes in the circuit path.