13 results about "Parasitic impedance" patented technology

A high power density integrated circuit module packaging method and its packaging structure belong to the field of microelectronic device packaging technology. In the inner cavity assembly area of the ceramic packaging shell, the chip assembly area is provided with a heat sink area and a functional area, the heat sink area and the functional area are provided as flat bottom pits, the power of the chips in the circuit is graded, a two-stage or more stepped structure is adopted, the chips are distributed from deep flat bottom pits to shallow flat bottom pits according to the power from large to small, the heat sink area is lower than the functional area, the power type chip with large power is assembled in the heat sink area, and the functional type chip with small power is assembled in the functional area. A metal through hole penetrating through the ceramic base body is arranged below the heat sink area or the functional area to realize shortest path heat dissipation and shortest path internal and external electrical connection. The problems of low power density, low integration, large parasitic impedance and parasitic inductance, low reliability and high application cost of the existing high-power devices (assemblies or modules) are solved. It is widely used in the field of high-reliability power integrated circuit module integration technology.

The invention relates to the technical field of semiconductors, and discloses a metal clamp and a lateral local carrier lifetime control method, and the metal clamp comprises a bracket which is used for accommodating a power device; the metal baffle is located in the bracket, a containing space is formed between the metal baffle and the bracket, the metal baffle comprises a step baffle, the height of a plurality of steps in the step baffle is determined by the target irradiation dose of a corresponding area in the power device, and the plurality of steps are non-obtuse-angle steps. On the basis of not changing the structure of the power device, the radiation dose penetrating through the metal is regulated and controlled through the stepped metal baffle plate, so that the service lives of minority carriers in different regions of the power device are finely designed, the switching-off speeds of the different regions of the power device are different, and the switching-off efficiency of the power device is improved. And turn-off inconsistency caused by parasitic impedance is offset, and turn-off current sharing and turn-off capability improvement are realized.

The utility model discloses a readout circuit, a readout system and a solid-state imaging device, and relates to the technical field of image sensor imaging reading. A negative impedance conversion circuit unit; and a charging and discharging acceleration circuit unit. By configuring the negative impedance conversion circuit unit and the charging and discharging acceleration circuit unit, on one hand, the negative impedance conversion circuit unit can utilize a source follower of the negative impedance conversion circuit unit and a connection mode of related circuit elements, an operational amplifier does not need to be used, and corresponding negative impedance can be generated to counteract parasitic impedance of the VSL; therefore, the small signal establishment speed is effectively accelerated. The defects that in the prior art, the dynamic range of the VSL is easily limited by increasing the bias current of the load current source circuit, and the performance of the circuit is easily deteriorated due to the fact that the VSL is reduced to a certain degree are effectively overcome. And on the other hand, the charging and discharging acceleration circuit unit provides a large transient current so as to accelerate the large signal establishment speed.

The utility model provides a glass substrate structure and a chip packaging structure, the glass substrate structure comprises at least two glass substrates, the two adjacent glass substrates are electrically connected through a conductive circuit and / or a conductive through hole, the traditional complex process of prefabricating a middle rewiring layer is abandoned, and the production cost is reduced. Through direct stacking without an intermediate layer between glass substrates and interconnection of conductive through holes / circuits, a three-dimensional packaging structure is realized, so that parasitic impedance brought by an intermediate layer is eliminated, interlayer thermal resistance is reduced, and signal transmission efficiency is optimized. Meanwhile, the packaging structure is filled with the conductive paste, the thermal expansion coefficient of the conductive paste is matched with the height of the glass substrate, interface thermal stress is reduced, layering failure under high-temperature circulation is avoided, and the reliability of the packaging structure is improved. And moreover, the conductive circuit and the conductive through hole are filled in a hole groove and slurry manner, so that the defect-free forming of the high-aspect-ratio through hole is realized, and the transmission loss of a high-frequency signal is reduced.

In one described example, a circuit includes a switching converter comprising a switch with a first current input, a second current input, and a control input, each of the first and second current inputs having an associated parasitic impedance. An energy harvesting circuit has a third input and a first output, the third input being coupled to each of the first and second current inputs. A voltage regulator has a fourth input and a second output, the fourth input being coupled to the first output or an input voltage terminal, and the second output being coupled to a voltage terminal of the circuit.

This disclosure is directed to a system and method for applying machine learning model to a PCB layout to obtain an estimate of the parasitic values of the board. The machine learning model may be trained with various PCB layouts to accurately determine an estimated parasitic impedance. Determine regions of the board having a high parasitic impedance value, alerting the user to reconfiguring the region so to achieve a desired range of values.

In a described example, a circuit includes a switching converter comprising a switch having a first current input, a second current input, and a control input, a respective one of the first current input and the second current input having an associated parasitic impedance. An energy capture circuit has a third input and a first output, in which the third input is coupled to the respective one of the first current input and the second current input. A voltage regulator has a fourth input and a second output, in which the fourth input is coupled to the first output or an input voltage terminal, and the second output is coupled to a voltage terminal of the circuit.

The invention relates to a switching energy capture circuit. In described examples, a circuit (100) includes a switching converter including a switch (102) having a first current input, a second current input, and a control input, a respective one of the first current input and the second current input having an associated parasitic impedance. An energy capture circuit (124) has a third input and a first output, wherein the third input is coupled to the respective one of the first current input and the second current input. A voltage regulator (132) has a fourth input and a second output, where the fourth input is coupled to the first output or input voltage terminal, and the second output is coupled to a voltage terminal of the circuit.

The invention provides a semiconductor device radio frequency modeling method and model for a silicon-on-insulator (SOI) platform. The method comprises the following steps: constructing an equivalent circuit model comprising a gate / body end parasitic impedance network, an intrinsic capacitance module, a body resistance module and a substrate network module; an intrinsic capacitance parameter is extracted through a low-frequency CV test, Cg is decomposed into overlapping capacitance, depletion capacitance and accumulation capacitance, and a hyperbolic tangent function and polynomial correction are introduced; extracting parasitic resistance inductance by using layout information and square resistance; bulk resistance parameters modulated by voltage are extracted based on the high-frequency S parameters, and the body resistance is fitted by adopting an exponential function. The model provided by the invention can accurately reflect the back gate effect and the bulk resistance modulation effect of the SOI device, and shows excellent fitting precision in a wide frequency band, wide voltage and wide temperature range.

The invention relates to the technical field of lithium ion testing, and discloses an electrochemical impedance spectroscopy-based lithium battery SOH fault monitoring method, which comprises the following steps of: firstly, acquiring a reference interface roughness parameter and a reference area amplification coefficient in a fault-free state under a set testing condition; applying an alternating current excitation signal to the lithium battery to be detected and collecting original impedance data; obtaining a de-noised interface impedance spectrum after high-frequency parasitic impedance stripping and de-noising reconstruction; a target frequency band with constant phase angle response is locked by calculating a derivative value of an impedance phase angle changing along with frequency; extracting an evolution slope of an imaginary part value in the frequency band, calculating a current interface roughness parameter and converting the current interface roughness parameter into a current area amplification coefficient; and finally, calculating a deviation value with a reference coefficient, and comparing the deviation value with a judgment threshold to output a monitoring result.

A measurement circuit (300) is provided. The measurement circuit (300) includes a control engine (320). An excitation source (302) is coupled to the control engine (320). A first electrode set (322, 326) and a second electrode set (324, 328) are coupled to the excitation source (302) and receive current from the excitation source (302). The control engine (320) operates the excitation source (302) in a first mode and a second mode. In the first mode, the control engine (320) measures a parasitic impedance associated with the first electrode set (322, 326) and the second electrode set (324, 328), and in the second mode, the control engine (320) measures an impedance of the first electrode set (322, 326) and the second electrode set (324, 328) and an impedance of an external object (350).

According to various embodiments, an electronic device may comprise: a biological body contact circuit including four electrodes; a current-voltage measurement module including a power supply port, a current measurement port, a first voltage measurement port, a second voltage measurement port, an alternating current signal generator electrically connected to the power supply port, an ammeter electrically connected to the current measurement port, and a voltmeter interposed between and electrically connected to the first voltage measurement port and the second voltage measurement port; a processor; a memory electrically connected to the processor to store the characteristic impedance values of circuit elements interposed between and electrically connected to the current-voltage measurement module and the biological body contact circuit, and to store values for parasitic impedance stemming from parasitic elements existing between the biological body contact circuit and a ground; and a current-voltage path configuration module configured to electrically connect the biological body contact circuit to the power supply port, the current measurement port, the first voltage measurement port, and the second voltage measurement port such that the voltage path and current path of the biological body contact circuit can be changed under control of the processor. Various other embodiments are also possible.

The invention relates to the technical field of integrated circuit electronic design automation, in particular to a digital circuit engineering simulation system. The system comprises a netlist reconstruction module, a current excitation module, a noise convolution module, a time sequence backfilling module and a risk assessment module. The system extracts parasitic impedance by analyzing a physical layout, and determines an independent power supply area; the core of the method is that instantaneous current and impedance characteristics are subjected to convolution to generate voltage drop, logic gate delay is subjected to nonlinear correction and backfilled to a scheduler, and meanwhile, a path robustness index is calculated according to dynamic delay to generate an evaluation signal; according to the method, the barrier between logic simulation and physical sign-off is broken, the conversion from discrete logic verification to physical perception continuous waveform simulation is realized, and the influence of physical topology on circuit behaviors can be truly reflected.