87 results about "Parasitic impedance" patented technology

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

An apparatus and method for a frequency based integrated circuit that selectively filters out unwanted bands or regions of interfering frequencies utilizing one or more tunable notch or bandpass filters or tunable low or high pass filters capable of operating across multiple frequencies and multiple bands in noisy RF environments. The tunable filters are fabricated within the same integrated circuit package as the associated frequency based circuitry, thus minimizing R, L, and C parasitic values, and also allowing residual and other parasitic impedance in the associated circuitry and IC package to be absorbed and compensated.

Electronic elements (44, 44′, 44″) having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44′, 44″) are scaled to higher power and / or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62′, 62″) having electrically isolated inclusions (65, 65′, 65′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78′, 78″) in which they are embedded and / or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65′, 65″) and silicon oxide for the dielectric material (78, 78′, 78″). The inclusions (65, 65′, 65″) preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78′, 78″).

An integrated circuit oscillator includes a microelectromechanical (MEM) resonator having input and output terminals. An oscillation sustaining circuit is provided. The oscillation sustaining circuit is electrically coupled between the input and output terminals of the microelectromechanical resonator. The oscillation sustaining circuit includes a sustaining amplifier and a negative impedance circuit electrically coupled to the sustaining amplifier. The negative impedance circuit is configured to increase a tuning range of the oscillator by at least partially cancelling a parasitic shunt capacitance associated with the microelectromechanical resonator.

In one embodiment, an IR drop analysis methodology may include characterizing standard cells without including power parasitic impedances, extracting the power parasitic impedances for the standard cells, and characterizing the standard cells with the power parasitic impedances. A set of timing parameters (such as minimum delays and maximum delays through the cells) may be generated from each characterization. The methodology may include comparing the timing parameters from each characterization, and identifying cells for which additional design effort should be expended to improve the power supply grid (e.g. to reduce the power parasitic impedances). For example, a margin may be budgeted for speed loss (delay increase) due to IR drop. If the difference in the timing parameters exceeds the margin, additional design effort may be warranted.