Compact semiconductor package with integrated bypass capacitor and method

Abstract

A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

Description

technical field [0001] The invention relates to the field of electronic system packaging. More precisely, the invention applies to physical level packaging of semiconductor wafers. Background technique [0002] Due to its high integration density, relatively low static leakage current and increasing power capacity, power MOSFETs are still widely used in power electronics such as switching power supplies and frequency converters. Moreover, power mosfets also have many very important characteristics, such as: increasing integration, decreasing package size and the consequent increasing requirements for heat dissipation in the consumer market. [0003] Listed below are some related prior art references in US application 12 / 326,065: [0004] "DirectFET" technology (US Patent 6,624,522, US Patent 7,285,866 and US Patent Application Publication 2007 / 0284722); [0005] US Patent 6,777,800 entitled "Semiconductor Chip Package Including Drain Clip"; [0006] U.S. application 11 / 7...

AI Technical Summary

Problems solved by technology

From the photos provided in the IEEE paper, although there are limited structural details about how the input capacitor Cin is mounted on the top of the system-in-package, there is no evidence that the system-in-package is used to increase the heat dissipation on the top of the input capacitor. The top exposure of the miniature contact holes outside the

Another conclusion is that the system-in-package described in the IEEE paper does not have extensive top exposure above the high-side and low-side MOSFET chips, except for the end of the input capacitor Cin.

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